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| The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. !" # $$$ (c) 2001 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BSI Certificate No. FM24653). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung- Eup Yongin-City, Kyunggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(31)-209-1907 FAX: (82)-(31)-209-1899 Home Page: http://www.intl.samsungsemi.com Printed in the Republic of Korea "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. The S3C8238/C8235/F8235 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8238/C8235/F8235 microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure Instruction Set Chapter 1, "Product Overview," is a high-level introduction to S3C8238/C8235/F8235 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the S3C8-series CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C8238/C8235/F8235 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II. Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the S3C-series microcontroller family and are reading this manual for the first time, we recommend that you first read Chapters 1-3 carefully. Then, briefly look over the detailed information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary. Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C8238/C8235/F8235 microcontroller. Also included in Part II are electrical, mechanical, Flash MCU, and development tools data. It has 16 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Clock Circuit RESET and Power-Down I/O Ports Basic Timer 8-bit Timer A/B 16-bit Timer 1 Watch Timer LCD Controller/Driver Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 10-bit Analog-to-Digital Converter Voltage Booster Voltage Level Detector Pattern Generation Module Electrical Data Mechanical Data S3F8235 Flash MCU Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C8238/C8235/F8235 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. !"#$$! S3C8-Series Microcontrollers ....................................................................................................................... 1-1 S3C8238/C8235/F8235 Microcontroller........................................................................................................ 1-1 Features........................................................................................................................................................ 1-2 Block Diagram .............................................................................................................................................. 1-3 Pin Assignment ............................................................................................................................................. 1-4 Pin Assignment ............................................................................................................................................. 1-5 Pin Assignment ............................................................................................................................................. 1-6 Pin Descriptions ............................................................................................................................................ 1-7 Pin Circuits ........................................................................................................................................... 1-9 Overview ....................................................................................................................................................... 2-1 Program Memory (ROM) .............................................................................................................................. 2-2 Smart Option ........................................................................................................................................ 2-3 Register Architecture .................................................................................................................................... 2-4 Register Page Pointer (PP) .................................................................................................................. 2-6 Register Set 1....................................................................................................................................... 2-7 Register Set 2....................................................................................................................................... 2-7 Prime Register Space .......................................................................................................................... 2-8 Working Registers................................................................................................................................ 2-9 Using The Register Points ................................................................................................................... 2-10 Register Addressing...................................................................................................................................... 2-12 Common Working Register Area (C0H-CFH) ..................................................................................... 2-14 4-Bit Working Register Addressing ...................................................................................................... 2-15 8-Bit Working Register Addressing ...................................................................................................... 2-17 System And User Stack ................................................................................................................................ 2-19 Overview ....................................................................................................................................................... 3-1 Register Addressing Mode (R)...................................................................................................................... 3-2 Indirect Register Addressing Mode (IR)........................................................................................................ 3-3 Indexed Addressing Mode (X) ...................................................................................................................... 3-7 Direct Address Mode (DA) ............................................................................................................................ 3-10 Indirect Address Mode (IA) ........................................................................................................................... 3-12 Relative Address Mode (RA) ........................................................................................................................ 3-13 Immediate Mode (IM) ........................................................................................................................... 3-14 Overview............................................................................................................................................... 4-1 Overview ....................................................................................................................................................... 5-1 Interrupt Types ..................................................................................................................................... 5-2 S3C8238/C8235 Interrupt Structure ..................................................................................................... 5-3 Interrupt Vector Addresses................................................................................................................... 5-5 Enable/Disable Interrupt Instructions (EI, DI) ....................................................................................... 5-7 System-Level Interrupt Control Registers............................................................................................. 5-7 Interrupt Processing Control Points...................................................................................................... 5-8 Peripheral Interrupt Control Registers .................................................................................................. 5-9 System Mode Register (SYM) .............................................................................................................. 5-10 Interrupt Mask Register (IMR) .............................................................................................................. 5-11 Interrupt Priority Register (IPR) ............................................................................................................ 5-12 Interrupt Request Register (IRQ).......................................................................................................... 5-14 Interrupt Pending Function Types ........................................................................................................ 5-15 Interrupt Source Polling Sequence....................................................................................................... 5-16 Interrupt Service Routines .................................................................................................................... 5-16 Generating Interrupt Vector Addresses ................................................................................................ 5-17 Nesting of Vectored Interrupts.............................................................................................................. 5-17 Overview ....................................................................................................................................................... 6-1 Data Types ........................................................................................................................................... 6-1 Register Addressing ............................................................................................................................. 6-1 Addressing Modes................................................................................................................................ 6-1 Flags Register (FLAGS) ....................................................................................................................... 6-6 Flag Descriptions.................................................................................................................................. 6-7 Instruction Set Notation ........................................................................................................................ 6-8 Condition Codes ................................................................................................................................... 6-12 Instruction Descriptions ........................................................................................................................ 6-13 ! " Overview ....................................................................................................................................................... 7-1 System Clock Circuit ............................................................................................................................ 7-1 Clock Status During Power-Down Modes ............................................................................................ 7-2 System Clock Control Register (CLKCON).......................................................................................... 7-3 # $$% &' System Reset................................................................................................................................................ 8-1 Overview .............................................................................................................................................. 8-1 Normal Mode Reset Operation ............................................................................................................ 8-1 Hardware Reset Values ....................................................................................................................... 8-2 Power-Down Modes...................................................................................................................................... 8-5 Stop Mode ............................................................................................................................................ 8-5 Idle Mode.............................................................................................................................................. 8-6 ( ) Overview ....................................................................................................................................................... 9-1 Port 1.................................................................................................................................................... 9-7 Port 2.................................................................................................................................................... 9-11 Port 3.................................................................................................................................................... 9-13 Port 4.................................................................................................................................................... 9-16 * +%, Overview ....................................................................................................................................................... 10-1 Basic Timer (BT) .................................................................................................................................. 10-1 Basic Timer Control Register (BTCON) ............................................................................................... 10-1 Basic Timer Function Description ........................................................................................................ 10-3 #&-%,)+ 8-Bit Timer A ................................................................................................................................................. 11-1 Overview .............................................................................................................................................. 11-1 Function Description ............................................................................................................................ 11-2 Timer A Control Register (TACON) ..................................................................................................... 11-3 Block Diagram...................................................................................................................................... 11-4 8-Bit Timer B ................................................................................................................................................. 11-5 Overview .............................................................................................................................................. 11-5 &- %, Overview ....................................................................................................................................................... 12-1 Function Description............................................................................................................................. 12-2 Timer 1 Control Register (T1CON)....................................................................................................... 12-3 Block Diagram ...................................................................................................................................... 12-4 .%, Overview ....................................................................................................................................................... 13-1 Watch Timer Control Register (WTCON: R/W) ................................................................................... 13-2 Watch Timer Circuit Diagram ............................................................................................................... 13-3 /')' Overview ....................................................................................................................................................... 14-1 LCD Circuit Diagram............................................................................................................................. 14-2 LCD RAM Address Area....................................................................................................................... 14-3 LCD Control Register (LCON), D0H..................................................................................................... 14-4 LCD Mode Register (LMOD) ................................................................................................................ 14-5 LCD Key Strobe Output Mode .............................................................................................................. 14-7 LCD Drive Voltage ................................................................................................................................ 14-8 LCD SEG/COM Signals........................................................................................................................ 14-8 LCD Voltage Driving Method ................................................................................................................ 14-14 *&-&&' Overview ....................................................................................................................................................... 15-1 Function Description...................................................................................................................................... 15-1 Conversion Timing................................................................................................................................ 15-2 A/D Converter Control Register (ADCON) ........................................................................................... 15-2 Internal Reference Voltage Levels ....................................................................................................... 15-3 Block Diagram ...................................................................................................................................... 15-4 0+ 16 Voltage Booster........................................................................................................................................ 16-1 Overview ....................................................................................................................................................... 16-1 Function Description...................................................................................................................................... 16-1 Block Diagram ............................................................................................................................................... 16-2 ! 0/' Overview ....................................................................................................................................................... 17-1 Voltage Level Detector Control Register (VLDCON) ........................................................................... 17-3 # 1 Overview ....................................................................................................................................................... 18-1 Pattern Gneration Flow ........................................................................................................................ 18-1 ( $' Overview .............................................................................................................................................. 19-1 * ' Overview .............................................................................................................................................. 20-1 2#2/34 Overview ....................................................................................................................................................... 21-1 Operating Mode Characteristics........................................................................................................... 21-6 ',% Overview ....................................................................................................................................................... 22-1 Shine .................................................................................................................................................... 22-1 SAMA Assembler ................................................................................................................................. 22-1 SASM88 ............................................................................................................................................... 22-1 HEX2ROM ........................................................................................................................................... 22-1 Target Boards ...................................................................................................................................... 22-1 TB8238/5 Target Board........................................................................................................................ 22-3 SMDS2+ Selection (SAM8) .................................................................................................................. 22-5 IDLE LED ............................................................................................................................................. 22-5 STOP LED ........................................................................................................................................... 22-5 % !" 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 & % !" S3C8238/C8235/F8235 Block Diagram ..................................................................... 1-3 S3C8238/C8235/F8235 Pin Assignment (64-SDIP) .................................................. 1-4 S3C8238/C8235/F8235 Pin Assignment (64-QFP) ................................................... 1-5 S3C8238/C8235/F8235 Pin Assignment (64-LQFP) ................................................. 1-6 Pin Circuit Type B () ........................................................................................ 1-9 Pin Circuit Type C ...................................................................................................... 1-9 Pin Circuit Type D-2 (P3) ........................................................................................... 1-9 Pin Circuit Type D-4 (P0.0-P0.7 except P0.4)........................................................... 1-9 Pin Circuit Type D-4" (P0.4) ....................................................................................... 1-10 Pin Circuit Type F-19 (P1.4-P1.7) .............................................................................. 1-10 Pin Circuit Type F-20 (P1.0-P1.3) .............................................................................. 1-11 Pin Circuit Type H (SEG/COM).................................................................................. 1-11 Pin Circuit Type H-4 ................................................................................................... 1-12 Pin Circuit Type H-14 (P2, P4) ................................................................................... 1-12 Program Memory Address Space.............................................................................. 2-2 Smart Option .............................................................................................................. 2-3 Internal Register File Organization............................................................................. 2-5 Register Page Pointer (PP)........................................................................................ 2-6 Set 1, Set 2, Prime Area Register, and LCD Data Register Map............................... 2-8 8-Byte Working Register Areas (Slices)..................................................................... 2-9 Contiguous 16-Byte Working Register Block ............................................................. 2-10 Non-Contiguous 16-Byte Working Register Block ..................................................... 2-11 16-Bit Register Pair .................................................................................................... 2-12 Register File Addressing ............................................................................................ 2-13 Common Working Register Area ............................................................................... 2-14 4-Bit Working Register Addressing ............................................................................ 2-16 4-Bit Working Register Addressing Example............................................................. 2-16 8-Bit Working Register Addressing ............................................................................ 2-17 8-Bit Working Register Addressing Example............................................................. 2-18 Stack Operations........................................................................................................ 2-19 Register Addressing................................................................................................... 3-2 Working Register Addressing .................................................................................... 3-2 Indirect Register Addressing to Register File............................................................. 3-3 Indirect Register Addressing to Program Memory ..................................................... 3-4 Indirect Working Register Addressing to Register File .............................................. 3-5 Indirect Working Register Addressing to Program or Data Memory.......................... 3-6 Indexed Addressing to Register File .......................................................................... 3-7 Indexed Addressing to Program or Data Memory with Short Offset .......................... 3-8 Indexed Addressing to Program or Data Memory...................................................... 3-9 Direct Addressing for Load Instructions ..................................................................... 3-10 Direct Addressing for Call and Jump Instructions ...................................................... 3-11 Indirect Addressing .................................................................................................... 3-12 Relative Addressing ................................................................................................... 3-13 Immediate Addressing ............................................................................................... 3-14 % !" 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 7-1 7-2 7-3 7-4 7-5 7-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 & % !" Register Description Format....................................................................................... 4-4 S3C8-Series Interrupt Types ...................................................................................... 5-2 S3C8238/C8235/F8235 Interrupt Structure................................................................ 5-4 ROM Vector Address Area......................................................................................... 5-5 Interrupt Function Diagram......................................................................................... 5-8 System Mode Register (SYM) .................................................................................... 5-10 Interrupt Mask Register (IMR) .................................................................................... 5-11 Interrupt Request Priority Groups............................................................................... 5-12 Interrupt Priority Register (IPR) .................................................................................. 5-13 Interrupt Request Register (IRQ) ............................................................................... 5-14 System Flags Register (FLAGS) ................................................................................ 6-6 Main Oscillator Circuit (Crystal or Ceramic Oscillator) ............................................... 7-1 Main Oscillator Circuit (RC Oscillator) ........................................................................ 7-1 System Clock Circuit Diagram.................................................................................... 7-2 System Clock Control Register (CLKCON) ................................................................ 7-3 Oscillator Control Register (OSCCON) ...................................................................... 7-4 STOP Control Register (STPCON) ............................................................................ 7-4 Port 0 High-Byte Control Register (P0CONH)............................................................ 9-4 Port 0 Low-Byte Control Register (P0CONL) ............................................................. 9-5 Port 0 Interrupt Control Register (P0INT)................................................................... 9-6 Port 0 Interrupt Pending Register (P0PND)................................................................ 9-6 Port 1 High-Byte Control Register (P1CONH)............................................................ 9-8 Port 1 Low-Byte Control Register (P1CONL) ............................................................. 9-9 Port 1 Pull-up Control Register (P1PUP).................................................................... 9-10 Port 2 High-Byte Control Register (P2CONH)............................................................ 9-11 Port 2 Low-Byte Control Register (P2CONL) ............................................................. 9-12 Port 3 Control Register (P3CON) ............................................................................... 9-14 Port 3 Interrupt Control Register (P3INT)................................................................... 9-15 Port 3 Interrupt Pending Register (P3PND)................................................................ 9-15 Port 4 Control Register (P4CON) ............................................................................... 9-16 % !" 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 13-1 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 15-1 15-2 15-3 15-4 16-1 16-2 & % !" Basic Timer Control Register (BTCON) ..................................................................... 10-2 Basic Timer Block Diagram........................................................................................ 10-4 Timer A Control Register (TACON) ........................................................................... 11-3 Timer A Functional Block Diagram ............................................................................ 11-4 Timer B Functional Block Diagram ............................................................................ 11-5 Timer B Control Register (TBCON) ........................................................................... 11-6 Timer B Registers ...................................................................................................... 11-6 Carrier on/off Control Register ................................................................................... 11-7 Timer 1 Control Register (T1CON) ............................................................................ 12-3 Timer 1 Functional Block Diagram............................................................................. 12-4 Watch Timer Circuit Diagram..................................................................................... 13-3 LCD Function Diagram............................................................................................... 14-1 LCD Circuit Diagram .................................................................................................. 14-2 LCD Display Data RAM Organization ........................................................................ 14-3 LCD Mode Contol Register ........................................................................................ 14-6 Key Strobe Contol Register........................................................................................ 14-7 Select/No-Select Bias Signals in Static Display Mode ............................................... 14-8 Select/No-Select Bias Signals in 1/4 Duty, 1/3 Bias Display Mode............................ 14-9 Select/No-Select Bias Signals in 1/8 Duty, 1/4 Bias Display Mode............................ 14-9 Key Input Check Sequence During Key Strobe Out Duration .................................... 14-10 Example of Key Strobe Mode with 1/4 Duty SEG Output ......................................... 14-11 LCD Signal and Wave Forms Example in 1/8 Duty, 1/4 Bias Display Mode ............. 14-12 LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode............ 14-13 Voltage Dividing Resistor Circuit Diagram ................................................................. 14-14 A/D Converter Control Register (ADCON) ................................................................. 15-2 A/D Conversion Interrupt Register (ADINT) ............................................................... 15-3 A/D Converter Data Register (ADDATAH/L).............................................................. 15-3 A/D Converter Functional Block Diagram .................................................................. 15-4 Voltage Booster Block Diagram ................................................................................. 16-2 Pin Connection Example............................................................................................ 16-2 % !" 17-1 17-2 17-2 18-1 18-2 18-3 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 20-2 20-3 21-1 21-2 21-3 21-4 21-5 22-1 22-2 22-3 22-4 & % !" VLD Control Register (VLDCON) ............................................................................... 17-1 Block Diagram for Voltage Level Detect..................................................................... 17-2 Voltage Level Detect Circuit and Control Register ..................................................... 17-3 Pattern Generation Flow............................................................................................. 18-1 PG Control Register (PGCON)................................................................................... 18-2 Pattern Generation Circuit Diagram ........................................................................... 18-2 Input Timing for External Interrupts (Ports 0) ............................................................. 19-5 Input Timing for .............................................................................................. 19-5 Stop Mode Release Timing Initiated by .......................................................... 19-6 Stop Mode(main) Release Timing Initiated by Interrupts ........................................... 19-7 Stop Mode(sub) Release Timing Initiated by Interrupts ............................................. 19-7 Recommended A/D Converter Circuit for Highest Absolute Accuracy....................... 19-9 Clock Timing Measurement at XIN ............................................................................ 19-11 LVR (Low Voltage Reset) Timing ............................................................................... 19-13 Operating Voltage Range ........................................................................................... 19-14 64-SDIP-750 Package Dimensions............................................................................ 20-1 64-QFP-1420F Package Dimensions......................................................................... 20-2 64-LQFP-1010-AN Package Dimensions................................................................... 20-3 S3F8235 Pin Assignments (64-SDIP Package) ......................................................... 21-2 S3F8235 Pin Assignments (64-QFP Package) .......................................................... 21-3 S3F8235 Pin Assignments (64-LQFP Package) ........................................................ 21-4 LVR (Low Voltage Reset) Timing ............................................................................... 21-9 Operating Voltage Range ........................................................................................... 21-10 SMDS Product Configuration (SMDS2+) ................................................................... 22-2 TB8238/5 Target Board Configuration ...................................................................... 22-3 40-Pin Connectors (J101, J102) for TB8238/5........................................................... 22-6 S3C8238/C8235/F8235 Probe Adapter Cables for 64-QFP Package ....................... 22-6 & !" 1-1 2-1 4-1 4-2 4-3 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 8-1 8-2 8-3 9-1 9-2 13-1 14-1 14-2 14-3 14-4 14-5 16-1 16-2 17-1 17-2 & % !" S3C8238/C8235/F8235 Pin Descriptions (64-SDIP) ................................................. 1-7 S3C8238/C8235/F8235 Register Type Summary...................................................... 2-3 Set 1 Registers........................................................................................................... 4-1 Set 1, Bank 0 Registers ............................................................................................. 4-2 Set 1, Bank 1 Registers ............................................................................................. 4-3 Interrupt Vectors......................................................................................................... 5-6 Interrupt Control Register Overview........................................................................... 5-7 Interrupt Source Control and Data Registers ............................................................. 5-9 Instruction Group Summary ....................................................................................... 6-2 Flag Notation Conventions ......................................................................................... 6-8 Instruction Set Symbols ............................................................................................. 6-8 Instruction Notation Conventions ............................................................................... 6-9 Opcode Quick Reference........................................................................................... 6-10 Condition Codes......................................................................................................... 6-12 S3F8235 Set 1 Register Values after (Mask ROM Mode) ............................. 8-2 S3F8235 Set 1, Bank 0 Register Values after (Mask ROM Mode)................ 8-3 S3F8235 Set 1, Bank 1 Register Values after (Mask ROM Mode)................ 8-4 S3C8238/C8235 Port Configuration Overview........................................................... 9-1 Port Data Register Summary ..................................................................................... 9-2 Watch Timer Control Register (WTCON): Set 1, Bank 1, FAH, R/W ........................ 13-2 LCD Control Register (LCON) Organization .............................................................. 14-4 LCD Mode register ..................................................................................................... 14-5 Frame Frequency according to LCD Clock Signal (LCDCK) ..................................... 14-5 Maximum Number of Display Digits per Duty Cycle .................................................. 14-6 LCD Drive Voltage Values ......................................................................................... 14-8 Voltage Booster Absolute Maximum Ratings............................................................. 16-3 Voltage Booster Electrical Characteristics ................................................................. 16-3 VLDCON Value and Detection Level ......................................................................... 17-3 Characteristics of Voltage Level Detect Circuit .......................................................... 17-4 & !" 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 21-1 21-2 21-3 21-4 21-5 22-1 22-2 22-3 & % !" Absolute Maximum Ratings........................................................................................ 19-2 D.C. Electrical Characteristics .................................................................................... 19-2 A.C. Electrical Characteristics .................................................................................... 19-5 Input/Output Capacitance........................................................................................... 19-6 Data Retention Supply Voltage in Stop Mode ............................................................ 19-6 A/D Converter Electrical Characteristics .................................................................... 19-8 Main Oscillator Frequency (f) ............................................................................. 19-10 Main Oscillator Clock Stabilization Time (t)........................................................... 19-10 ub Oscillator Frequency (f) ................................................................................. 19-11 Sub Oscillator(crystal) Stabilization Time (t) ......................................................... 19-11 Analog Circuit Characteristics and Consumed Current.............................................. 19-12 LVR(Low Voltage Reset) Circuit Characteristics ....................................................... 19-13 Descriptions of Pins Used to Read/Write the EPROM............................................... 21-5 Comparison of S3F8235 and S3C8235 Features ...................................................... 21-5 Operating Mode Selection Criteria ............................................................................. 21-6 D.C Electrical Characteristics ..................................................................................... 21-6 LVR(Low Voltage Reset) Circuit Characteristics ....................................................... 21-9 Power Selection Settings for TB8238/5...................................................................... 22-4 Power Selection Settings for EVA CHIP Operation (For using SMDS2+ only) .......... 22-4 The SMDS2+ Tool Selection Setting.......................................................................... 22-5 ' ( )( # *++( % !" Using the Page Pointer for RAM clear (Page 0, Page 1).............................................................................. 2-6 Setting the Register Pointers ........................................................................................................................ 2-10 Using the RPs to Calculate the Sum of a Series of Registers ...................................................................... 2-11 Addressing the Common Working Register Area......................................................................................... 2-15 Standard Stack Operations Using PUSH and POP...................................................................................... 2-20 )( # & "* Using the Timer A ......................................................................................................................................... 11-8 Using the Timer B ......................................................................................................................................... 11-9 )( # , ( & " Using the Timer 1 ......................................................................................................................................... 12-5 )( # - )& " Using the Watch Timer ................................................................................................................................. 13-4 )( .# /' ' Using the LCD Display.................................................................................................................................. 14-15 Using the LCD Key Strobe and Display ........................................................................................................ 14-17 )( # $ *% & ' % Using the ADC Interrupt................................................................................................................................ 15-5 Using the ADC Main Routine ........................................................................................................................ 15-6 )( 0# 1 %/' Using the Voltage Level Detector ................................................................................................................. 17-5 )( # 2 + Using the Pattern Generation ....................................................................................................................... 18-3 % 3+ 4 ADCON ADINT BTCON CLKCON FLAGS IMR IPH IPL IPR IRQ KSCON LCON LMOD OSCCON P0CONH P0CONL P0INT P0PND P1CONH P1CONL P1PUR P2CONH P2CONL P3CON P3INT P3PND P4CON PGCON % !" % !" A/D Converter Control Register ..................................................................................4-5 A/D Conversion Interrupt Register ..............................................................................4-6 Basic Timer Control Register......................................................................................4-7 System Clock Control Register ...................................................................................4-8 System Flags Register................................................................................................4-9 Interrupt Mask Register ..............................................................................................4-10 Instruction Pointer (High Byte) ...................................................................................4-11 Instruction Pointer (Low Byte) ....................................................................................4-11 Interrupt Priority Register ............................................................................................4-12 Interrupt Request Register..........................................................................................4-13 Key Strobe Control Register .......................................................................................4-14 LCD Control Register..................................................................................................4-15 LCD Mode Control Register........................................................................................4-16 Oscillator Control Register ..........................................................................................4-17 Port 0 Control Register (High Byte) ............................................................................4-18 Port 0 Control Register (Low Byte) .............................................................................4-19 Port 0 Interrupt Control Register .................................................................................4-20 Port 0 Interrupt Pending Register ...............................................................................4-21 Port 1 Control Register (High Byte) ............................................................................4-22 Port 1 Control Register (Low Byte) .............................................................................4-23 Port 1 Pull-up Control Register ...................................................................................4-24 Port 2 Control Register (High Byte) ............................................................................4-25 Port 2 Control Register (Low Byte) .............................................................................4-26 Port 3 Control Register ...............................................................................................4-27 Port 3 Interrupt Control Register .................................................................................4-28 Port 3 Interrupt Pending Register ...............................................................................4-29 Port 4 Control Register ...............................................................................................4-30 Pattern Generation Control Register...........................................................................4-31 % 3+ 4 PP RP0 RP1 SPH SPL STPCON SYM T1CON TACON TBCON TINTPND VLDCON WTCON % !" % !" Register Page Pointer ................................................................................................ 4-32 Register Pointer 0....................................................................................................... 4-33 Register Pointer 1....................................................................................................... 4-33 Stack Pointer (High Byte) ........................................................................................... 4-34 Stack Pointer (Low Byte)............................................................................................ 4-34 Stop Control Register ................................................................................................. 4-35 System Mode Register ............................................................................................... 4-36 Timer 1 Control Register ............................................................................................ 4-37 Timer A Control Register............................................................................................ 4-38 Timer B Control Register............................................................................................ 4-39 Timer A,1 Interrupt Pending Register......................................................................... 4-40 Voltage Level Detector Control Register .................................................................... 4-41 Watch Timer Control Register.................................................................................... 4-42 3 " ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB % !" % !" Add with Carry.............................................................................................................6-14 Add..............................................................................................................................6-15 Logical AND ................................................................................................................6-16 Bit AND .......................................................................................................................6-17 Bit Compare ................................................................................................................6-18 Bit Complement ..........................................................................................................6-19 Bit Reset .....................................................................................................................6-20 Bit Set .........................................................................................................................6-21 Bit OR .........................................................................................................................6-22 Bit Test, Jump Relative on False ................................................................................6-23 Bit Test, Jump Relative on True .................................................................................6-24 Bit XOR .......................................................................................................................6-25 Call Procedure ............................................................................................................6-26 Complement Carry Flag..............................................................................................6-27 Clear ...........................................................................................................................6-28 Complement ...............................................................................................................6-29 Compare .....................................................................................................................6-30 Compare, Increment, and Jump on Equal..................................................................6-31 Compare, Increment, and Jump on Non-Equal ..........................................................6-32 Decimal Adjust............................................................................................................6-33 Decrement ..................................................................................................................6-35 Decrement Word ........................................................................................................6-36 Disable Interrupts........................................................................................................6-37 Divide (Unsigned) .......................................................................................................6-38 Decrement and Jump if Non-Zero ..............................................................................6-39 Enable Interrupts.........................................................................................................6-40 Enter ...........................................................................................................................6-41 Exit ..............................................................................................................................6-42 Idle Operation .............................................................................................................6-43 Increment....................................................................................................................6-44 Increment Word ..........................................................................................................6-45 Interrupt Return...........................................................................................................6-46 Jump ...........................................................................................................................6-47 Jump Relative .............................................................................................................6-48 Load ............................................................................................................................6-49 Load Bit.......................................................................................................................6-51 3 " LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR % !" % !" Load Memory ............................................................................................................. 6-52 Load Memory and Decrement.................................................................................... 6-54 Load Memory and Increment ..................................................................................... 6-55 Load Memory with Pre-Decrement ............................................................................ 6-56 Load Memory with Pre-Increment .............................................................................. 6-57 Load Word.................................................................................................................. 6-58 Multiply (Unsigned)..................................................................................................... 6-59 Next ............................................................................................................................ 6-60 No Operation .............................................................................................................. 6-61 Logical OR.................................................................................................................. 6-62 Pop from Stack........................................................................................................... 6-63 Pop User Stack (Decrementing) ................................................................................ 6-64 Pop User Stack (Incrementing) .................................................................................. 6-65 Push to Stack ............................................................................................................. 6-66 Push User Stack (Decrementing) .............................................................................. 6-67 Push User Stack (Incrementing) ................................................................................ 6-68 Reset Carry Flag ........................................................................................................ 6-69 Return......................................................................................................................... 6-70 Rotate Left.................................................................................................................. 6-71 Rotate Left through Carry........................................................................................... 6-72 Rotate Right ............................................................................................................... 6-73 Rotate Right through Carry ........................................................................................ 6-74 Select Bank 0 ............................................................................................................. 6-75 Select Bank 1 ............................................................................................................. 6-76 Subtract with Carry..................................................................................................... 6-77 Set Carry Flag ............................................................................................................ 6-78 Shift Right Arithmetic.................................................................................................. 6-79 Set Register Pointer ................................................................................................... 6-80 Stop Operation ........................................................................................................... 6-81 Subtract ...................................................................................................................... 6-82 Swap Nibbles ............................................................................................................. 6-83 Test Complement under Mask................................................................................... 6-84 Test under Mask ........................................................................................................ 6-85 Wait for Interrupt ........................................................................................................ 6-86 Logical Exclusive OR ................................................................................................. 6-87 Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. The major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode released by interrupt or reset -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. The S3C8238/C8235/F8235 single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based on Samsung's latest CPU architecture. The S3C8235 is a microcontroller with a 16K-byte mask-programmable ROM embedded. The S3F8235 is a microcontroller with a 16K-byte Flash ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C8238/C8235/F8235 by integrating the following peripheral modules with the powerful SAM8 core: -- Five programmable I/O ports, including three 8-bit ports and two 4-bit ports, for a total of 32 pins. -- Eight bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). -- Two 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- Watch timer for real time -- 8-channel A/D converter The S3C8238/C8235/F8235 is versatile microcontroller for camera, LCD and ADC application, etc. They are currently available in 64-pin LQFP, 64-pin QFP and 64-pin SDIP package. * * * SAM88RC CPU core Real-time and interval time measurement. Clock generation for LCD. * * 16K-bytes ROM 632 -bytes RAM !""# * 8(4)COM X 24SEG (MAX 24 digit) * * * "# * * Crystal, Ceramic, RC Crystal for subsystem clock CPU clock divider (1/1, 1/2, 1/8, 1/16) Eight analog input channels 20us conversion speed at 10MHz f clock. $% * * * * LCD drive voltage supply S/W control (Enable/Disable) 78 instructions IDLE and STOP instructions added for powerdown modes !&$%' (!$') * * Low Voltage Check to make system reset V = 2.2V/2.6V/3.6V * 400 ns at 10-MHz f (minimum) * * * * 16 interrupt sources with 16 vector. 8 level, 16 vector interrupt structure * Pattern generation module triggered by timer match signal and S/W. $%" + Voltage Detector to indicate specific voltage. S/W control (2.4V, 2.7V, 3.3V, 4.5V) * * Total 32 bit-programmable pins , - * * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer function One 8-bit timer/counter () with three operating modes; Interval mode, capture mode and PWM mode. One 8-bit timer/counter () Carrier frequency (or PWM) generator. One 16-bit capture timer/counter () with two operating modes; Interval mode, Capture mode for pulse period or duty. Support automatic key strobe output with LCD driver(Maximum 4 x 12 key matrices). %'% * * -40C to + 85C %$%'% * * * 2.0 V to 5.5 V at 4 MHz f (Preliminary) .% * 64 pin SDIP, 64 pin QFP, 64 pin LQFP * Low Voltage Reset(LVR) level and enable/disable are at your hardwired option. (ROM address 3E,3FH) (2((20 73!(3!08 . . 2(20 7)()08 ( 454! 454! RESET ) ! 2(20 " #"$!"% *2(!& *2! *2! (20! (2! (2!! (2+!& " !"% " !"% " !"% &$'!"% * *2(*2* + +2(+2* .,.,+ (0 1( 1 1 1* 3(3* .,.,+ ,) )"- # % ./ # ,. %" 1 " 2+20+2(+2* *2*6 /%01234233425/3425 ."% ., ., .,* .,+ *2(!&!!3( *2!3 *2!3 *2*63* (2(3!( (23! (23! (2*3!* (2+!&3!+ . . 4 4 ! ! 4! 4! RESET (2!!3! (2!3! (20!3!0 . . 2()( 2) 2) 2*)* * + 0 9 ( * + 0 9 ( * + 0 9 *( * * + * ( 9 0 + * ( +9 + +0 + + ++ +* + + +( *9 * *0 * * *+ ** 1*+2*10! 1+21! 1+21!( 1(+2(1+!9 1920! 12!0 102! 12+! 12*!+ 1+2!* 1*2! 12(! 1 1( 19 1 10 1 1 1+ 1* 1 1 1( ( * +20)01* 2)1 2)1 02+)+1( /%041234233425/3425 %(670") *2!3 *2!3 *2*63* (2(3!( (23! (23! (2*3!* (2+!&3!+ . . 4 4 ! ! 4! 4! RESET (2!!3! (2!3! (20!3!0 * + 0 9 ( * + 0 9 ( +9 + +0 + + ++ +* + + +( *9 * *0 * * *+ ** 102! 12+! 12*!+ 1+2!* 1*2! 12(! 1 1( 19 1 10 1 1 1+ 1* 1 1 1( ( /%021234233425/3425 %(6708/) *2!3 *2!3 *2*63* (2(3!( (23! (23! (2*3!* (2+!&3!+ . . 4 4 ! ! 4! 4! RESET * + 0 9 ( * + /%071234233425/3425 %(670!8/) + +0 + + ++ +* + + +( *9 * *0 * * *+ ** 1+2!* 1*2! 12(! 1 1( 19 1 10 1 1 1+ 1* 1 1 1( ( -01234233425/3425" (670") 9 P0.0-P0.7 I/O " I/O port with bit-programmable pins. Configurable to schmitt trigger input mode or output mode by software. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. P0.4 pin have high current drive capability. P1.0-P1.3 I/O port with bit-programmable pins. Configurable to normal input and AD input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. Pullup resistors are assignable by software. I/O port with bit-programmable pins. Configurable to normal input and AD input mode and push-pull output. Pull-up resistors are assignable by software. Alternately configurable to output pins for LCD COM and PG output. I/O port with bit-programmable pins. Configurable to normal input mode or output mode. Pin circuits are either push-pull or nchannel open-drain type. Pull-up resistors are assignable by software. Alternately configurable to output pins for LCD SEG and Key strobe. I/O port with bit-programmable pins. Configurable to schmitt trigger input mode, push-pull output mode. The port 3 pins have high current drive capability. F-20 29-32 AD0-AD3 D-4 D-4" 91 11-14, 24-26 15 / External Interrupt (INT0-INT7) TBPWM T1OUT T1CK T1CAP P1.4-P1.7 F-19 33-36 AD4-AD7 COM7-COM4 PG3-PG0 P2.0-P2.7 H-14 53 - 60 SEG12-SEG 19 KSTR1-KSTR 8 P3.0-P3.3 D-4 7-10 TAPWM TACK TACAP BUZ KIN0-KIN3 -01234233425/3425" (670")() 9 P4.0-4.3 I/O " I/O port with bit-programmable pins. Configurable to normal input mode and push-pull output mode. pull-up resistors are assignable by software. Alternately configurable to output pins for LCD SEG and PG output. The port 4 pins have high current drive capability. A/D converter analog input channels A/D converter reference voltage A/D converter Ground Capacitor terminal for voltage booster O LCD Common signal output LCD Common signal output LCD Segment signal output LCD Segment signal output LCD Segment signal output LCD power supply Remote controller signal output(Carrier output) or PWM output TimerA PWM output I TimerA Capture input TimerA Clock source input Key strobe input System Reset pin O I I O O I - - Timer1 match toggle output Timer1 clock source input Timer1 Capture input Pattern generation output Pattern generation output Test signal input pin (for factory use only; must be connected to V). Power supply input pin Ground pin H F-19 H H-14 H-14 - D-4" D-2 D-2 D-2 D-4 B D-4 D-4 D-4 F-19 H-14 - - - H-14 91 61-64 / SEG20-SEG23 KSTR9-KSTR 12 AD0-AD7 AV AV CA,CB COM0-COM3 COM4-COM7 SEG0-SEG 11 SEG12-SEG19 SEG20-SEG23 VLC1-VLC4 TBPWM TAPWM TACAP TACK KIN0-KIN3 RESET T1OUT T1CK T1CAP PG0-PG3 PG4-PG7 TEST V V I F-20 F-19 - 29-36 28 27 5, 6 37-40 33-36 41-52 53-60 61-64 1-4 15 7 9 8 7-10 23 24 25 26 33-36 61-64 20 16 17 P1.0-P1.7 - P1.4-P1.7 - P2.0-P2.7 KSTR1-KSTR8 P4.0-P4.3 KSTR9-KSTR12 - P0.4 P3.0 P3.2 P3.1 P3.0-P3.3 - P0.5 P0.6 P0.7 P1.4-P1.7 P4.0-P4.3 - - - . . #"# $'%"!"// ) )"# " "$ " ! /%051 () /%0:1 "04(2) . . . ) ' )"# 3' ;23! 3% ) )"# " "$ " ! 3"# :" /%061 /%031 "07 (;1;0;1: ;17) . (2+) ! <= " <<7(2+8 4 )"# . " "$ " ! ;23! 3% 3"# :" /%0<1 "07=(;17) . . )" 3 ) 3> ,) 3 1 )"# ) 3 3% ) "$ " ! >+ > /%0;1 /0<(1701:) . ) )"# ) 3 ) !) "$ " ! /%01 /04;(1;012) . . 1 . . /%041 >(*) . . 1 )"# . . /%021 >07 . . )" 3 ) 3> ,) 3 1 )"# "$ " ! > > /%071 >07(4?7) The S3C8238/C8235/F8235 microcontroller has two types of address space: -- Internal program memory (ROM) -- Internal data memory (RAM) A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C8238/C8235/F8235 has an internal 8/16-Kbyte mask-programmable ROM and 632-byte RAM. Program memory (ROM) stores program codes or table data. The S3C8238 has 8 Kbytes of internal maskprogrammable program memory. The S3C8235/F8235 has 16 Kbytes of internal mask programmable program memory. The program memory address range is therefore 0H-3FFFH (see Figure 2-1). The first 256 bytes of the ROM (0H-0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H. !" ##$% & '#(# # )% '" *)+(,,#-- + /0 / / / / / / / . 6' $-, # )% '" *)+(,,#-- + /0 / / / / / / / . 6' $-, .&*1- '"2 3 4 /& 4/& 54/& .&*"22 3 4"2.&* 4-2.&* Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from 003EH to 003FH. The S3C8235/C8238/F8235 only use 003EH. The default value of ROM is FFH (LVR disable) In the S3C8238/C8235/F8235 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In addition, set 2 is logically expanded 2 separately addressable register pages, page 0-page 1. In case of S3C8238/C8235/F8235 the total number of addressable 8-bit registers is 632. Of these 632 registers, 16 bytes are for CPU and system control registers, 24 bytes are for LCD data registers, 64 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 512 registers are for generalpurpose use. You can always address set 1 register locations, regardless of which of the 2 register pages is currently selected. Set 1 locations, however, can only be addressed using direct addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. !"#!#$"#!%$#!% General-purpose registers (including the 16-byte common working register area, two 192-byte prime register area, and two 64-byte set 2 area) LCD data registers CPU and system control registers Mapped clock, peripheral, I/O control, and data registers ' &' 528 24 16 64 632 - ", 9#%;#'" #'*7- #*7- #(,,#--"7+', - 8"#9$#%'- *7- #!",# *7- # !",5, +', ", : )%# '"- - - ", 9#%;#'" #'*7- #*7- #(,,#--"7+', 8"#9$#%'-*7- # *7- #(,,#--"7+', 0 9# *7- #((,,#--"7+',- - .-%*7- # ! ( )*) *) )+ , The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C8238/C8235/F8235 microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. *7- #979'" #99 *< + /0 / / / / / / / . - " '"#7- #%7- '"2 -3 - " '"397 '$##7- #%7- '"2 -3 '$#397 !" ; #''" #'# %7- ",#%" ,/ (;#,=##- '%# '"=# - ;2 ,- " '"",-'$#1$--;'=" 2'1 ' ;#7- #%7%'" #/>;-1$--;'$,2',?, ',,#-' ;#%7-/ - + , ** ./0 & + 12 , LD SRP LD CLR DJNZ CLR LD LD CLR DJNZ CLR PP,#00H #0C0H R0,#0FFH @R0 R0,RAMCL0 @R0 PP,#10H R0,#0FFH @R0 R0,RAMCL1 @R0 ; Destination 0, Source 0 ; Page 0 RAM clear starts ; R0 = 00H ; Destination 1, Source 0 ; Page 1 RAM clear starts ; R0 = 00H RAMCL0 RAMCL1 )*)) The term set 1 refers to the upper 64 bytes of the register file, locations C0H-FFH. The upper 32-byte area of this 64-byte space (E0H-FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H-FFH) contains 48 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H-DFH) and a 16-byte common working register area (C0H-CFH). Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") )*)) The same 64-byte physical space that is used for set 1 locations C0H-FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3C8328/C8325/F8235, the set 2 address range (C0H-FFH) is accessible on pages 0-1. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area is commonly used for stack operations. ))*) ") The lower 192 bytes (00H-BFH) of the S3C8238/C8235/F8235's two 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, or 1 you must set the register page pointer (PP) to the appropriate source and destination values. 9@",-- '" #' 8"#%$#%'- 9#%;#",!) ., #7- # 9# % 0 . *7- #(# % 22 23"44 56*)*) Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 328-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: -- One working register slice is 8 bytes (eight 8-bit working registers, R0-R7 or R8-R15) -- One working register block is 16 bytes (sixteen 8-bit working registers, R0-R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H-CFH). *9 *7- #-** ;#7- #%'" #%'" - ' '"2 -'? ;#7- # -% - "7 ' 2 ='#:"7#7- #2':/ 0 )" *9*7- #-**0 0 7#'5 8+ , /*9))*) After a reset, RP# point to the working register common area: RP0 points to addresses C0H-C7H, and RP1 points to addresses C8H-CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-6 and 2-7). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H-FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-6). Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. ** .0 SRP SRP1 SRP0 CLR LD #70H #48H #0A0H RP0 RP1,#0F8H ; ; ; ; ; RP0 RP0 RP0 RP0 RP0 70H, RP1 78H no change, RP1 48H, A0H, RP1 no change 00H, RP1 no change no change, RP1 0F8H *7- # '" "- *9 *9 * 0 * '" 7$'$<'#:"7 *7- #2': :" 7'5 8' 8 *0 * '" 7$'$<'#:"7 *7- #2': 0* * *9 *9 *7- # '" "- - # " 7'5 8' 8 ** ./0 " 0 & & Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively: SRP0 ADD ADC ADC ADC ADC #80H R0,R1 R0,R2 R0,R3 R0,R4 R0,R5 ; ; ; ; ; ; RP0 80H R0 R0 + R0 R0 + R0 R0 + R0 R0 + R0 R0 + R1 R2 + C R3 + C R4 + C R5 + C The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD ADC ADC ADC ADC 80H,81H 80H,82H 80H,83H 80H,84H 80H,85H ; ; ; ; ; 80H 80H 80H 80H 80H (80H) (80H) (80H) (80H) (80H) + + + + + (81H) (82H) (83H) (84H) (85H) + + + + C C C C Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles. The S3C-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space. + *" . *"A "41",,#-- ; 7' %9$#%'-*7- # $#$% !"#" !"# $!#" &"' !"#" 8"#9$#%'-*7- # ;#7- #%'" #*9"",%"," %'" ''"'? ;2 B--B'? ;#7- #? ' ;# ;"- /(? ##- *9%'" - ' ' '"-0",*9 '' '"- ; - ' ;''"='#:"7#7- ##/ !" ; #''" #'# %7-#%" ,/97- '" "'? ;,,#--2#7- #-" ;" #"#7- #?/ #!' !"#" ( !"#" 97 *7- #(,,#--"7)" 97 !",# *7- # ( ( !",5, (,,#--"7 (,,#--"7 (,,#--"7 +',+',+',"29'" , ' #7- #9'" # "29'" ,2*7- #9'" # 1 "56*)*))+"19<"9, After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H- CFH, as the active 16-byte working register block: RP0 C0H-C7H RP1 C8H-CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. ''="7;#,=##- #7- # %'" #-*9",*9 %'" ' ; ''"='#:"7#7- ## ' '"-/ 9# % 0 . *7- #(# *94 *9 4 " 5 8 ** .0" 5 8 As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. )= 1. LD SRP LD 2. ADD 0C2H,40H #0C0H R2,40H 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: ; R2 (C2H) the value in location 40H ; Invalid addressing mode! Use working register addressing instead: SRP ADD #0C0H R3,#45H ; R3 (C3H) R3 + 45H -'56*)*)44)* Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: -- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). -- The five high-order bits in the register pointer select an 8-byte slice of the register space. -- The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B). "&* "&+ ) "&*"&+ $ %&'%( " # # ! ,! # ! ! -'5 8 "&* *+++* *** ) "&* "&+ *++++ *** *+++* ++* " -./0 " *++* %&'%( +++* 1 21'"2 !-'5 8)= #'56*)*)44)* You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing. As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the three low-order bits of the complete address are provided by the original instruction. Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH (10101011B). "&* "&+ ) "&*"&+ $ ! ! 3 ! " # # ! ! ! -#'5 8 "&* *++** *** ) "&+ "&+ +*+*+ *** "++ ++**+*++ ! 24"++5"62 +*+*+ *++ " -*$7/0 ) 3 %#'5 8)= The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C8238/C8235 architecture supports stack operations in the internal register file. 8 Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-16. +!, **#"" &'4 3 &'/ 3 &'4 &'/ 8 ) 3 ($) **#"" ) 3 78 /4&8 You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. 8 + 32 9, Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C8238/C8235/F8235, the SPL must be initialized to an 8-bit value in the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H". ** .8 / /9 The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) PUSH PUSH PUSH PUSH PP RP0 RP1 R3 ; ; ; ; Stack address 0FEH Stack address 0FDH Stack address 0FCH Stack address 0FBH PP RP0 RP1 R3 POP POP POP POP R3 RP1 RP0 PP ; ; ; ; R3 Stack address 0FBH RP1 Stack address 0FCH RP0 Stack address 0FDH PP Stack address 0FEH -- Register (R) -- Indexed (X) Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: -- Indirect Register (IR) -- Direct Address (DA) -- Indirect Address (IA) -- Relative Address (RA) -- Immediate (IM) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2). ) * ! " # $ %&' $ '( )"4 55 " (. , , ) * + & , $. ! " # -/0 %&' -0 ' * . , 1 23"4 ' & , -(! In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H-FFH in set 1 using the Indirect Register addressing mode. ) * ! "" ( * " # 3 6"7 $ %&' "7 $ '( ) * ( ) * 9 "$ -:4 ) * ) * " # 33 8 60 60 ,! *. 2 2 !$ 1 !$ *+ &-. $ !"#$% &'( ) /!## "#$ 0 )"4 5 5 " ( . , , 0 & , -(+! 3"4" -:4 * * ) * + & , ( ' ) * ) * ) * ) * " # 3 3 3 ;/6: 2/6-+ 6+/ % * % * % * ! Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H-FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented. 5 - ) * $. 4 < 23"4 (' &, -(! A " ( . , , " # 35/=4">-? %&' 4" @ "# ,! *. 2 2 !$ 1 !$ *+ ,,5 3$ 4 0?59. ) . -.!$ . *+ *+ ) . 0 /!## "#$ ) . !"#$% - - '62 78 9: '62 78 9: ;59=2 7 ! > ;"$! -4 !'4$ 4! +$$> $# !%&'&()) ,! *. 2 2 !$ 1 !$ *+ ,,5 ,,5 $ 3$ 0?59. ) . -.!$ . *+ *+ ) . 0 /!## "#$ ) . !"#$% - - '622278 9: '622278 9: ;59=2227 ! > ;"$! -4 !'4$ 4! +$$> *# ! In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. ) * ) * D 4* 3. 4* < B5B B-B ) * D 3"4" ) * ) *# B5BC ) * B-BC) * " # 3 3 ;/-02+7 ;/-02+7 %$'@ ' -02+7! ;1 % 3 /' * 1 +! ), ) * ) * D D 4* 3. 4* " # 8 33 /84 "3E %&' 84- -: %&' "3E -: ! )-./ In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. ) * 3"4)F 3. 4* D 4* ) * 3 50;; " # 33 =+57 %$'-: @ * +57 +-7 ' 1 In Relative Address (RA) mode, a twos-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR. ) * ) * D " " # 8 D3$/GH"$ %&' "$ @ ' H-0I-0 0 In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. ) * $' @ ' ! " # 35/=57 Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C8238/C8235/F8235 register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "and Power-Down." LCD control register LCD mode register Basic timer control register Clock Control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer LCON LMOD BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP 208 209 211 222 213 214 215 216 217 218 219 220 221 222 223 D0H D1H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Location D2H is not mapped. ! Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 0 interrupt control register Port 0 interrupt pending register Port 3 interrupt control register Port 3 interrupt pending register Timer A/Timer 1 interrupt pending register Timer A control register Timer A counter register Timer A data register Timer B control register Timer B data register(high byte) Timer B data register(low byte) Key strobe data register Voltage level detector control register Watch timer control register Oscillator control register STOP Control register Pattern generation control register Pattern generation data register A/D converter control register A/D converter data register(high byte) A/D converter data register(low byte) AD interrupt register Carrier on/off control register Basic timer counter data register Interrupt priority register P0 P1 P2 P3 P4 P0INT P0PND P3INT P3PND TINTPND TACON TACNT TADATA TBCON TBDATAH TBDATAL KSDATA VLDCON WTCON OSCCON STPCON PGCON PGDATA ADCON ADDATAH ADDATAL ADINT REMCON BTCNT IPR 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 253 255 E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FDH FFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Location FCH is factory use only. Location FEH is not mapped. " Port 0 control High register Port 0 control Low register Port 1 pull-up control register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control register Port 4 control register Key strobe control register P0CONH P0CONL P1PUR P1CONH P1CONL P2CONH P2CONL P3CON P4CON KSCON 224 225 227 228 229 230 231 232 234 235 E0H E1H E3H E4H E5H E6H E7H E8H EAH EBH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Location E1H is not mapped. Location E9H is not mapped. Locations ECH-EFH are not mapped. Location F0H is factory use only. Timer 1 control register Timer 1 counter register(high byte) Timer 1 counter register(low byte) Timer 1 data register 1(high byte) Timer 1 data register 1(low byte) Timer 1 data register 2(high byte) Timer 1 data register 2(low byte) Timer 1 prescaler register T1CON T1CNTH T1CNTL T1DATA1H T1DATA1L T1DATA2H T1DATA2L T1PS 241 242 243 244 245 246 247 248 F1H F2H F3H F4H F5H F6H F7H F8H R/W R R R/W R/W R/W R/W R/W Locations F9H-FFH are not mapped. + " , # ) %) " "#$% &$#'# RESET () %*#$ "#$+%% ,,#& -!% ' ' % % ' . ' % % % % . ) ) . ) / ! ' ' . * # . * #& ' ' . # 01+2'2" . # 01+22" !" -) ))) RESET # $ %& # '()* () + $ 01++/ (1++' #$ % # &' ( ,$ ' -''' ) * " ! !"# ! 0 R/W ) - - * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W 0 R/W Register addressing mode only Not used for the S3C8238/C8235/F8235, Always logic zero -&%$ . 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 -/& $% 0 0 1 ADC interrupt disable ADC interrupt enable / $ 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/4 fxx 0 0 1 Disable operation Start operation # $% &' ( ,$ ' -''' ) ! & $% .' 102/3 0 1 Interrupt is not pending (When reading) Clear pending bit (When writing) Interrupt is pending (When reading) Not used for the S3C8238/C8235/F8235 ) - - * - - + - - - - " - - - - - - !" ! 0 R/W Register addressing mode only &' ( ,$ ' -''' ) " ! !&'( ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W ) 0 R/W 0 R/W ! 0 R/W Register addressing mode only 4'#$ /'1(5 3 1 0 1 0 Disable watchdog timer function Enable watchdog timer function Others &%$ / 0 0 1 1 0 1 0 1 fxx/4096 fxx/1024 fxx/128 Not used /$ / 0 1 No effect Clear the basic timer counter value / #6$57'/ ( 0 1 No effect Clear both clock frequency dividers / !" # $ % & % $# ' !" # $ % ( #)) *# + , ,- *(&" &' ( ,$ ' -''' ) + " ! /.8/ 15 / 3 0 0 1 1 0 1 0 1 fxx/16 fxx/8 fxx/2 fxx/1 (non-divided) ) 0 - * 0 - + 0 - 0 R/W " 0 R/W + 0 - 0 - ! 0 - Register addressing mode only Not used for the S3C8238/C8235/F8235 (always logic zero) Not used for the S3C8238/C8235/F8235 (always logic zero) / .# *+ /- *# *% %% % 01(012 *(! &' ( ,$ ' -''' ) ) x R/W * x R/W + x R/W x R/W " x R/W , x R/W 0 R ! 0 R/W Register addressing mode only /5#1/3 0 1 Operation does not generate a carry or underflow condition Operation generates a carry-out or underflow into high-order bit 7 * 9#193 0 1 Operation result is a non-zero value Operation result is zero + #13 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") 27(:#1,3 0 1 Operation result is +127 or -128 Operation result is > +127 or < -128 " -';$ #13 0 1 Add operation completed Subtraction operation completed (/5#13 0 1 No carry-out of bit 3 or no underflow into bit 3 by addition or subtraction Addition generated carry-out of bit 3 or subtraction generated underflow into bit 3 # & $% $#1#&3 0 1 Interrupt return (IRET) in progress (when read) Fast interrupt service routine in progress (when read) ! -'' #1-3 0 1 Bank 0 is selected Bank 1 is selected 0 $%-!" &' ( ,$ ' -''' ) * + " ! ) x R/W * x R/W + x R/W x R/W " x R/W x R/W x R/W ! x R/W Register addressing mode only & $% <7)1& =)30 >?5 & $% 0 1 Disable (mask) Enable (un-mask) & $% <7*1& =*30 >-& $% 0 1 Disable (mask) Enable (un-mask) & $% <7+1& =+30 > 427(: 0 1 Disable (mask) Enable (un-mask) & $% <71& =30 >0 & $% .! .! ) 0 1 Disable (mask) Enable (un-mask) & $% <7"1& ="30 >0 & $% .! !.! " 0 1 Disable (mask) Enable (un-mask) & $% <71& =30 > 4/% $27(: 0 1 Disable (mask) Enable (un-mask) & $% <71& =30 >8'(: 0 1 Disable (mask) Enable (un-mask) & $% <7!1& =!30 >- 4/% $27(: 0 1 Disable (mask) Enable (un-mask) / % * % ' $ 345 . $&./0 &' ( ,$ ' -''' )@ ! ) x R/W * x *1 + x R/W x R/W " x R/W x R/W x R/W ! x R/W R/W Register addressing mode only & $ . -''145 3 The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15-IP8). The lower byte of the IP address is located in the IPL register (DBH). $&./2 &' ( ,$ ' -''' )@ ! ) x R/W x *1 * + x R/W x R/W " x R/W x R/W x R/W ! x R/W R/W Register addressing mode only & $ . -''1<:5 3 The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7-IP0). The upper byte of the IP address is located in the IPH register (DAH). $%.* &' ( ,$ ' -''' ) ' ) x R/W * x R/W + x R/W x R/W " x R/W x R/W !"# x R/W ! x R/W Register addressing mode only . 5/ (& $% A$%-'/ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Group priority undefined B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B Group priority undefined * + " ! & $% $$%/. 5/ 0 1 IRQ6 > IRQ7 IRQ7 > IRQ6 & $% A$%/. 5/ 0 1 IRQ5 > (IRQ6, IRQ7) (IRQ6, IRQ7) > IRQ5 & $% $$%. 5/ 0 1 IRQ3 > IRQ4 IRQ4 > IRQ3 & $% A$%. 5/ 0 1 IRQ2 > (IRQ3, IRQ4) (IRQ3, IRQ4) > IRQ2 & $% A$%-. 5/ 0 1 IRQ0 > IRQ1 IRQ1 > IRQ0 $%3$ &' ( ,$ ' -''' ) * + " ! + 0 R 0 R " 0 R 0 R 0 R ! 0 R ) 0 R * 0 R Register addressing mode only <7)1& =)3 6$ .' >?5 & $% 0 1 Not pending Pending <7*1& =*3 6$ .' >-& $% 0 1 Not pending Pending <7+1& =+3 6$ .' > 427(: 0 1 Not pending Pending <71& =3 6$ .' >.! .! )0 & $% 0 1 Not pending Pending <7"1& ="3 6$ .' >.! !.! "0 & $% 0 1 Not pending Pending <71& =3 6$ .' > 4/% $27(: 0 1 Not pending Pending <71& =3 6$ .' >8'(: 0 1 Not pending Pending <7!1& =!3 6$ .' >- 4/% $27(: 0 1 Not pending Pending 4* 5 &' ( ,$ ' -''' ) * + " ! / 6)77 0 R/W " 0 R/W 0 R/W !" 0 R/W ! 0 R/W ) 0 R/W * - - + - - Register addressing mode only ?5 0 0 1 Key Strobe output disable Key Strobe output enable Not used for the S3C8238/C8235/F8235 $ 0 1 45 sec (1.5 clock) 61 sec (2.0 clock) & 7 0 0 1 1 0 1 0 1 1 msec (32 clock) 2 msec (64 clock) 3 msec (96 clock) 4 msec (128 clock) ?5 2$ %$ . 0 0 1 0 1 x P4.0-P4.3 P2.4-P2.7 and P4.0-P4.3 P2.0-P2.7 and P4.0-P4.3 &' ( ,$ ' -''' ) + " ! ) 0 R/W * 0 R/W + 0 R/W - - " 0 R/W # 0 R/W 0 R/W ! 0 R/W Register addressing mode only Internal CAP bias; display off (Low signal output through COM/SEG) Internal CAP bias; display on (Valid signal output through COM/SEG) External register bias; booster off; display on (Valid signal output though COM/SEG) -6 &' ( ,$ ' -''' ) * + " ! $ 5' 0 0 1 0 1 x 1/8 duty, 1/4 bias 1/4 duty, 1/3 bias Static ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W 0 R/W ! 0 R/W Register addressing mode only &! &' ( ,$ ' -''' ) " ! 5 / 0 1 Main oscillator select Subsystem oscillator select Not used for the S3C8238/C8235/F8235 $5 2 / 0 1 Sub system oscillator RUN Sub system oscillator STOP 5 2 / 0 1 Main System Oscillator RUN Main System Oscillator STOP Not used for the S3C8238/C8235/F8235 ) 0 - * 0 - + 0 - 0 - " 0 R/W ) 0 R/W !"# 0 - ! 0 R/W Register addressing mode only .#/0 &' ( ,$ ' -''' ) * +@ "@ @ ! *1 0 R/W " 0 R/W # 0 R/W !" 0 R/W ! 0 R/W ) 0 R/W * 0 R/W + 0 R/W Register addressing mode only .! )/-.&) 0 0 1 1 0 1 0 1 Input mode; (both edge interrupt or T1CAP input - rising start) Input mode, pull-up; (falling edge interrupt) Push-pull output Input mode (T1CAP input - falling start) .! */?&* 0 0 1 1 0 1 0 1 Input mode; (both edge interrupt or T1CK input) Input mode, pull-up; (falling edge interrup or T1CK input) Push-pull output Push-pull output .! +28&+ 0 0 1 1 0 1 0 1 Input mode; (both edge interrupt) Input mode, pull-up; (falling edge interrupt) Push-pull output Alternative function; T1OUT .! .& 0 0 1 1 0 1 0 1 Input mode; (both edge interrupt) Input mode, pull-up; (falling edge interrupt) Push-pull output Alternative function; TBPWM .#/2 &' ( ,$ ' -''' )@ * +@ "@ @ ! .! !&! 0 0 1 1 0 1 0 1 .! & 0 0 1 1 0 1 0 1 .! & 0 0 1 1 0 1 0 1 .! "&" 0 0 1 1 0 1 0 1 ) 0 R/W * 0 R/W + 0 R/W *1 0 R/W " 0 R/W 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only Input mode; interrupt on rising edge Input mode, pull-up; interrupt on falling edge Input mode; interrupt on both edge Push-pull output Input mode; interrupt on rising edge Input mode, pull-up; interrupt on falling edge Input mode; interrupt on both edge Push-pull output Input mode; interrupt on rising edge Input mode, pull-up; interrupt on falling edge Input mode; interrupt on both edge Push-pull output Input mode; interrupt on rising edge Input mode, pull-up; interrupt on falling edge Input mode; interrupt on both edge Push-pull output 0 .#$% &' ( Value ' -''' ) ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W , 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only .! )0 & $% 1&)30 0 1 Disable interrupt Enable interrupt * .! *0 & $% 1&*30 0 1 Disable interrupt Enable interrupt + .! +0 & $% 1&+30 0 1 Disable interrupt Enable interrupt .! 0 & $% 1&30 0 1 Disable interrupt Enable interrupt " .! "0 & $% 1&"30 0 1 Disable interrupt Enable interrupt .! 0 & $% 1&30 0 1 Disable interrupt Enable interrupt .! 0 & $% 1&30 0 1 Disable interrupt Enable interrupt ! .! !0 & $% 1&!30 0 1 Disable interrupt Enable interrupt . .#$%.6 &' ( Value ' -''' ) ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 7 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only .! ).)& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending * .! *.*& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending + .! +.+& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .! .& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending " .! "."& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .! .& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending .! .& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending ! .! !.!& $% .' 0 1 Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending ./0 &' ( ,$ ' -''' ) * + " ! . .A!-/2) 0 0 1 1 0 1 0 1 Input mode . +.A-+/2* 0 0 1 1 0 1 0 1 Input mode . *.A-*/2+ 0 0 1 1 0 1 0 1 Input mode . ).A"-)/2 0 0 1 1 0 1 0 1 Input mode ) 0 R/W * 0 R/W + 0 R/W *1 0 R/W " 0 R/W + 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only AD7 converter input; Normal input off Push-pull output (COM4 output enable) Alternative function; PG3 output AD6 converter input; Normal input off Push-pull output (COM5 output enable) Alternative function; PG2 output AD5 converter input; Normal input off Push-pull output (COM6 output enable) Alternative function; PG1 output AD4 converter input; Normal input off Push-pull output (COM7 output enable) Alternative function; PG0 output / 4 #% 8 % ./2 &' ( ,$ ' -''' ) * + " ! . !-! 0 0 1 1 0 1 0 1 Input mode . - 0 0 1 1 0 1 0 1 Input mode . - 0 0 1 1 0 1 0 1 Input mode . "-" 0 0 1 1 0 1 0 1 Input mode ) 0 R/W * 0 R/W + 0 R/W *1 0 R/W " 0 R/W , 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only AD3 input; Normal input off Push-pull output Open-drain output AD2 input; Normal input off Push-pull output Open-drain output AD1 input; Normal input off Push-pull output Open-drain output AD0 input; Normal input off Push-pull output Open-drain output / 4 #% 8 % ..$ $% &' ( Value ' -''' ) ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W ) 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only . ).$$% 0 0 1 Pull-up disable Pull-up enable * . *.$$% 0 0 1 Pull-up disable Pull-up enable + . +.$$% 0 0 1 Pull-up disable Pull-up enable . .$$% 0 0 1 Pull-up disable Pull-up enable " . ".$$% 0 0 1 Pull-up disable Pull-up enable . .$$% 0 0 1 Pull-up disable Pull-up enable . .$$% 0 0 1 Pull-up disable Pull-up enable ! . !.$$% 0 0 1 Pull-up disable Pull-up enable / 9 4 % 8 % 4 # $ % %8 % .8/0 &' ( ,$ ' -''' )@ * + "@ @ ! *1 0 R/W " 0 R/W 7 0 R/W !" 0 R/W ! 0 R/W ) 0 R/W * 0 R/W + 0 R/W Register addressing mode only . )0AB? C 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output (SEG19/Key strobe, KSTR8 output enable) Open-drain output (SEG19/Key strobe, KSTR8 output enable) . *0AC? ) 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output (SEG18/Key strobe, KSTR7 output enable) Open-drain output (SEG18/Key strobe, KSTR7 output enable) . +0A)? * 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output (SEG17/Key strobe, KSTR6 output enable) Open-drain output (SEG17/Key strobe, KSTR6 output enable) . 0A*? + 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up Push-pull output (SEG16/Key strobe, KSTR5 output enable) Open-drain output (SEG16/Key strobe, KSTR5 output enable) .8/2 &' ( ,$ ' -''' ) * + " ! . !0A? 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up . 0A"? 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up . 0A? " 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up . "0A+? 0 0 1 1 0 1 0 1 Input mode Input mode, pull-up ) 0 R/W * 0 R/W + 0 R/W *1 0 R/W " 0 R/W 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only Push-pull output (SEG15/Key strobe, KSTR4 output enable) Open-drain output (SEG15/Key strobe, KSTR4 output enable) Push-pull output (SEG14/Key strobe, KSTR3 output enable) Open-drain output (SEG14/Key strobe, KSTR3 output enable) Push-pull output (SEG13/Key strobe, KSTR2 output enable) Open-drain output (SEG13/Key strobe, KSTR2 output enable) Push-pull output (SEG12/Key strobe, KSTR1 output enable) Open-drain output (SEG12/Key strobe, KSTR1 output enable) .) &' ( ,$ ' -''' ) * ." "89?&" 0 0 1 1 0 1 0 1 Inputmode; External Interrupt Watch timer; Buzzer output Push-pull output ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 9 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only Alternative mode; KIN3 input; Only falling edge interrupt (When key strobe output is enable (KSCON.7 = 1), port status is highimpedence during interval and pull-up during strobe out) + ." -/-.?& 0 1 1 x 0 1 Inputmode; External Interrupt (TACAP input) Push-pull output Alternative mode; KIN2 (When key strobe output is enable (KSCON.7 = 1), port status is highimpedence during interval and pull-up during strobe out) " ." -/??& 0 1 1 x 0 1 Inputmode; External Interrupt (TACAP input) Push-pull output Alternative mode; KIN1 (When key strobe output is enable (KSCON.7 = 1), port status is highimpedence during interval and pull-up during strobe out) ! ." !-.-28?&! 0 0 1 1 0 1 0 1 Inputmode; External Interrupt TAPWM or TAOUT output Push-pull output Alternative mode; KIN0 (When key strobe output is enable (KSCON.7 = 1), port status is highimpedence during interval and pull-up during strobe out) .)$% &' ( ,$ ' -''' ) * + " ! ." !?&!& $% 0 0 1 1 x 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge ." ?&& $% 0 0 1 1 x 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge ." ?&& $% 0 0 1 1 x 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge ." "?&"& $% 0 0 1 1 x 0 1 Interrupt Disable Interrupt Enable; falling edge Interrupt Enable; rising edge ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only / % 4( $*8 % +1" 8(- # $$ % .)$%.6 &' ( ,$ ' -''' ) " ! ." !?&!& $% .' 0 1 ." ?&& $% .' 0 1 ." ?&& $% .' 0 1 ." "?&"& $% .' 0 1 Not used for the S3C8238/C8235/F8235 ) - - * - - + - - - - " 0 R/W 9 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending / % 4( $*8 % +1" 8(- # $$ % 0 .+ &' ( ,$ ' -''' ) * + " ! . !0A!.A? B 0 0 1 1 0 1 0 1 Input mode . 0A.A+? ! 0 0 1 1 0 1 0 1 Input mode . 0A.A*? 0 0 1 1 0 1 0 1 Input mode . "0A".A)? 0 0 1 1 0 1 0 1 Input mode ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W !" 0 R/W 0 R/W ! 0 R/W Register addressing mode only Input mode, pull-up Push-pull output (SEG23/Key strobe, KSTR12 output enable) Alternative function; PG7 output Input mode, pull-up Push-pull output (SEG22/Key strobe, KSTR11 output enable) Alternative function; PG6 output Input mode, pull-up Push-pull output (SEG21/Key strobe, KSTR10 output enable) Alternative function; PG5 output Input mode, pull-up Push-pull output (SEG20/Key strobe, KSTR9 output enable) Alternative function; PG4 output . .!! &' ( ,$ ' -''' ) " ! , " 0 R/W 0 R/W !"# 0 R/W ! 0 R/W ) - - * - - + - - - - Register addressing mode only Not used for the S3C8238/C8235/F8235 0 1 No effect S/W trigger start (Auto clear) .A2% 0 0 1 PG operation disable PG operation enable .A2% ' 0 0 1 1 0 1 0 1 Timer A match siganal triggering Timer B underflow siganal triggering Timer 1 match siganal triggering S/W triggering mode .!. &' ( ,$ ' -''' ) ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W 0 R/W ! 0 R/W Register addressing mode only . 0 0 0 0 0 0 0 0 1 0 1 0 Destination: page 0 Destination: page 1 Destination: page 2 " ! $ . 0 0 0 0 0 0 0 0 1 0 1 0 Source: page 0 Source: page 1 Source: page 2 / ",(:&(:;:&(<;=:&(< $ # # $ %$+4$ 8&- %$ 8 # $ % % $ # %$& # 0> $ $ % % $ .# &' ( ,$ ' -''' ) " . !-'',$ ) 1 R/W * 1 R/W + 0 R/W 0 R/W " 0 R/W 7 - - - - ! - - Register addressing only Register pointer 0 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H-C7H. Not used for the S3C8238/C8235/F8235 ! . &' ( ,$ ' -''' ) " . -'',$ ) 1 R/W * 1 R/W + 0 R/W 0 R/W " 1 R/W - - - - ! - - Register addressing only Register pointer 1 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H-CFH. Not used for the S3C8238/C8235/F8235 ! !&"./0 &' ( ,$ ' -''' )@ ! ) x R/W *1 * x R/W + x R/W x R/W " x R/W 9 x R/W x R/W ! x R/W Register addressing mode only . -''145 3 The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15-SP8). The lower byte of the stack pointer value is located in register SPL (D9H). The SP value is undefined following a reset. !&"./2 &' ( ,$ ' -''' )@ ! ) x R/W *1 * x R/W + x R/W x R/W " x R/W : x R/W x R/W ! x R/W Register addressing mode only . -''1<:5 3 The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7-SP0). The upper byte of the stack pointer value is located in register SPH (D8H). The SP value is undefined following a reset. % &' ( ,$ ' -''' )@ ! ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W + 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only 2./ 10100101 Other values Enable stop instruction Disable stop instruction ,4 / # ) $,4 9 ,4 $ ) *(-6 &' ( ,$ ' -''' ) * ! A& $% 0 0 1 Disable global interrupt processing Enable global interrupt processing Not used for the S3C8238/C8235/F8235 Not used, always logic zero ) 0 R/W * - - + - - x - " x - x - 0 - ! 0 R/W Register addressing mode only / = $ $ %% $) $?" + $ ,9@ - '( &' ( ,$ ' -''' ) + " ! 27(:& $% 0 0 1 Disable overflow interrupt Enable overflow interrupt 4/% $& $% 0 0 1 Disable interrupt Enable interrupt /$ 0 0 1 No effect Clear the timer 1 counter (Auto-clear bit) 2% ' 0 0 1 1 0 1 0 1 Interval mode &%$ / 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x fxx/1 fxx/8 fxx/64 T1CK TBUF Counter Stop ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W !" 0 R/W ! 0 R/W Register addressing mode only Capture mode (Capture on falling edge, OVF can occur) Capture mode (Capture on rising edge, OVF can occur) Capture mode (Capture on both edge, OVF can occur) '( &' ( ,$ ' -''' ) * + " ! + 0 R/W 0 R/W " 0 R/W 0 R/W !"# 0 R/W ! - - ) 0 R/W * 0 R/W Register addressing mode only -&%$ / 0 0 1 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 External clock (TACK) -2% ' 0 0 1 1 0 1 0 1 Internal mode (TAOUT mode) Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF interrupt can occur) -/$ / 0 1 No effect Clear the timer A counter (After clearing, return to zero) -27(:& $% 0 0 1 Disable overflow interrupt Enable overflow interrupt - 4/% $& $% 0 0 1 Disable interrupt Enable interrupt Not used for the S3C8238/C8235/F8235 '( &' ( ,$ ' -''' )@ * +@ " ! ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only &%$ / 0 0 1 1 0 1 0 1 fxx fxx/2 fxx/4 fxx/8 & $% 0 0 1 1 0 1 0 1 Elapsed time for low data value Elapsed time for high data value Elapsed time for low and high data values Invalid setting & $% 0 0 1 Disable Interrupt Enable Interrupt % 0 1 Stop timer B Start timer B ' 0 1 One-shot mode Repeating mode 2$ %$ (%(%/ 0 1 T-FF is low T-FF is high / #)) *# 0 '( $%.6 &' ( ,$ ' -''' ) " ! Not used for the S3C8238/C8235/F8235 27(:& $% .' 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending ) - - * - - + - - - - " 0 R/W : 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only 4/% $& $% .' 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending -27(:& $% .' 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending - 4/% $& $% .' 0 0 1 No interrupt pending Clear pending bit when write Interrupt pending . !& &' ( ,$ ' -''' ) " ! (, 0 0 1 1 0 1 0 1 V = 2.4 V V = 2.7 V V = 3.3 V V = 4.5 V ,<2% 0 0 1 Operation off Operation on ,<<7 0 1 V is higher than reference voltage V is lower than reference voltage Not used for the S3C8238/C8235/F8235 ) 0 - * 0 - + 0 - 0 R/W " 0 R 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only !&0'( &' ( ,$ ' -''' ) * +@ "@ ! 4/ 0 1 Main system clock divided by 2 (fxx/128) Sub system clock (fxt) 4& $% 0 0 1 Disable watch timer interrupt Enable watch timer interrupt ) 0 R/W * 0 R/W + 0 R/W 0 R/W " 0 R/W 8 0 R/W !"# 0 R/W ! 0 R/W Register addressing mode only $DD 0 0 1 1 0 1 0 1 0.5 kHz buzzer (BUZ) signal output 1 kHz buzzer (BUZ) signal output 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output 4%' 0 0 1 1 0 1 0 1 1.0 s Interval 0.5 s Interval 0.25 s Interval 3.91 ms Interval 40 0 1 Disable watch timer; Clear frequency dividing circuits Enable watch timer 4& $% .' 0 1 Interrupt is not pending, Clear pending bit when write Interrupt is pending The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources. Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0-IRQ7, also called level 0-level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3C8238/C8235/F8235 interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels. Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C8238/C8235/F8235 uses sixteen vectors. A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3C8238/C8235/F8235 interrupt structure, there are sixteen possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit. The three components of the S3C8 interrupt structure described before -- levels, vectors, and sources -- are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: Type 2: Type 3: One level (IRQn) + one vector (V) + one source (S) One level (IRQn) + one vector (V) + multiple sources (S - S) One level (IRQn) + multiple vectors (V - V) + multiple sources (S - S, S- S) In the S3C8238/C8235/F8235 microcontroller, two interrupt types are implemented. ! ! "!# " $ % !"! #$#$# The S3C8238/C8235/F8235 microcontroller supports sixteen interrupt sources. All sixteen of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this devicespecific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware). When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. - *+, +-, +, +0, +1, +, / )!) / ( . ( )!) ( 2- - 2- 2- 2- 2- 0 2- " 2- 1 2- 3 &) ( /* 4% #$% ,!&$ !& ,!&$ !& ,!& ,!&$ !& ,!&$ !& !& !& !& !& !& !& !& !& !& ,!&$ !& !& +/, +, ++, 0 #-, #, #0, #1, " 1 3 #, #/, #+, ! & ' $ ( ) ' % # $ *+, ' % +-, ( - ( ) )% + '' % ' ' '$ ' )' ) ' ' # #$#$# ! " %&'' All interrupt vector addresses for the S3C8238/C8235/F8235 interrupt structure are stored in the vector address area of the internal 32-Kbyte ROM, 0H-7FFFH (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses). The program reset address in the ROM is 0100H. 5*) 6 1$ 0 1;4% 5,+76 ###, $8 ;4% 2' 9 % 5:96 / ###, "" - ) / / --, ##, RESET / --, %( &))&* *+ ! &)) '-* * 254 250 248 246 244 242 240 238 236 234 232 230 228 226 220 218 ./ * FEH FAH F8H F6H F4H F2H F0H EEH ECH EAH E8H E6H E4H E2H E0H DEH AD Interrupt Watch tiner overflow P0.7 external interrupt P0.6 external interrupt P0.5 external interrupt P0.4 external interrupt P0.3 external interrupt P0.2 external interrupt P0.1 external interrupt P0.0 external interrupt Timer 1 overflow Timer 1 match/capture Timer B underflow Timer A overflow Timer A match/capture IRQ1 IRQ0 IRQ2 IRQ3 ! Key strobe interrupt , ! IRQ7 IRQ6 IRQ5 IRQ4 " - - - 3 2 1 0 3 2 1 0 1 0 - 1 0 $* .$0 $0 ! & &1$' &1 % 23'4 Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. % The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure. During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. (%%5 In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: -- The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels. -- The interrupt priority register, IPR, controls the relative priorities of interrupt levels. -- The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). -- The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented). *+# ! %6 Interrupt mask register Interrupt priority register ' IMR IPR $0 R/W R/W '! Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0-IRQ7. Controls the relative processing priorities of the interrupt levels. The seven levels of S3C8238/C8235/F8235 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7. This register contains a request pending bit for each interrupt level. This register enables/disables fast interrupt processing, dynamic global interrupt processing, and external interface control (An external memory interface is implemented in the S3C8238/C8235/F8235 microcontroller). Interrupt request register System mode register IRQ SYM R R/W ! !" # # $ % ' % 5%%% Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: -- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) -- Interrupt level enable/disable settings (IMR register) -- Interrupt level priority settings (IPR register) -- Interrupt source enable/disable settings in the corresponding peripheral control registers % When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. + RESET -;3$ < ' 5;%6 2' %) 2% ' ) %) 9= ' > 5+$ * ?9 6 7 ! '**- .&%%5 For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). *+ ! * )'** ! Timer A overflow Timer A match/capture ! IRQ0 24 TINTPND TACON TACNT TADATA Timer B underflow Timer 1 overflow Timer 1 match/capture IRQ1 IRQ2 TBCON TBDATAH, TBDATAL TINTPND T1CON T1CNTH T1CNTL T1DATA1H T1DATA1L T1DATA2H T1DATA2L T1PS P0.3 external interrupt P0.2 external interrupt P0.1 external interrupt P0.0 external interrupt P0.7 external interrupt P0.6 external interrupt P0.5 external interrupt P0.4 external interrupt Watch timer overflow AD Interrupt IRQ5 IRQ6 WTCON ADCON ADDATAH ADDATAL ADINT P1CONH P1CONL Key strobe interrupt IRQ7 KSCON KSDATA F2H, bank 0 F7H, bank 0 F8H, bank 0 F9H, bank 0 FAH, bank 0 E4H, bank 1 E5H, bank 1 EBH, bank 1 F0H, bank 0 IRQ4 P0CONH P0INT P0PND E0H, bank 1 E5H, bank 0 E6H, bank 0 IRQ3 P0CONL P0INT P0PND * 24 E9H, bank 0 EAH, bank 0 EBH, bank 0 ECH, bank 0 EDH, bank 0 EEH, EFH, bank 0 E9H, bank 0 F1H, bank 1 F2H, bank 1 F3H, bank 1 F4H, bank 1 F5H, bank 1 F6H, bank 1 F7H, bank 1 F8H, bank 1 E1H, bank 1 E5H, bank 0 E6H, bank 0 ( ((%'5 2 (4 The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing (see Figure 5-5). A reset clears SYM.0 to "0". The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose. % 9 ' 5?96 *+, $ $ !& 9. 3 1 " 0 @. A > B - C * ' )' C + ' )' "-( )2 (4 ) (& 85 2(4 The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode. 9= ' 596 **, $ $ !& 9. 3 1 " 0 @. 0 " 3 1 D - C * D C + D - 9 !(*:2(4 %5 24 The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware). To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A Group B Group C IRQ0, IRQ1 IRQ2, IRQ3, IRQ3 IRQ5, IRQ6, IRQ7 2 > / 2 > . 2 > / / . . . . 0 " 1 3 - ; !, "5 ! As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: -- IPR.5 controls the relative priorities of group C interrupts. -- Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C. -- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. 2% ' 526 #+, $ $ .= -$ !& 9. > %B *3 *0 * - - - C F - - C . E E / - - C / E . E - C . E / E - - C E / E . - C E . E / - C / E E . C F 3 1 " 0 @. > / - C - E C E > . - C E 5$ 06 C 5$ 06 E ' . - C E 0 C 0 E > - C " E 51$ 36 C 51$ 36 E " ' - C 1 E 3 C 3 E 1 ! "24 < 5 2<4 You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to "0". You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled. < ' 56 *, $ $ 9. 3 1 " 0 @. " 0 3 1 - D < ' - C D ' C D ' = !, 2<4 " '5% %6 There are two types of interrupt pending bits: one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other must be cleared in the interrupt service routine by software. ) 1*)& -**"+".*)6* For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C8238/C8235/F8235 interrupt structure, the timer B underflow interrupt (IRQ1) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. ) 1*)+"> The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source's mode or control register. In the S3C8238/C8235/F8235 interrupt structure, pending conditions for IRQ3, IRQ4 and IRQ7 must be cleared in the interrupt service routine. %%5 < The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the source's interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. The CPU continues polling for interrupt requests. % Before an interrupt request is serviced, the following conditions must be met: -- Interrupt processing must be globally enabled (EI, SYM.0 = "1") -- The interrupt level must be enabled (IMR register) -- The interrupt level must have the highest priority if more than one levels are currently requesting service -- The interrupt must be enabled at the interrupt's source (peripheral control register) When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. 2. Save the program counter (PC) and status flags to the system stack. 3. Branch to the interrupt vector to fetch the address of the service routine. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request. & 5&5%&'' The interrupt vector area in the ROM (00H-FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4. Fetch the service routine's high-byte address from the vector location. 5. Fetch the service routine's low-byte address from the vector location. 6. Branch to the service routine specified by the concatenated 16-bit vector address. % A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H-FFH. 5%%' It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps: 1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). 2. Load the IMR register with a new mask value that enables only the higher priority interrupt. 3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR). 5. Execute an IRET. Depending on the application, you may be able to simplify the procedure above to some extent. ' ! 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'L,2M) > < B 8>.$8 $)/ 7 7 7 :7 $'+ /$ 6$ ;/; $') (/ $') 7 7 7 7 7 7 4$')/++' 4$')1 +/' $ - $')( 1 +/' $+/)& 2$ % ; ! < :&9 / "&9 / "&9 8,8 " &!828 ,(< , < > < E" 92K2?!9,K24?!94K,?!22?K4+?!2,?K24?! 24?K4? :&9 :&9 :&9 :&9 :&9 92!9, 92!I9, 22?!2,? 22?!I2,? 22?!J56? 92K25?!9,K24? 92K2=6?!9,K24?!24?K4? 922?K4N?!2,?K24? 922?K2?!2,?K24?! 24?K4? 922?K.? Q )! 4 %! 6 - - - - " $5>& +4 + +6 +5 +- "" " " 9 9 9 9 $9 $; %<1 .< 828P < P =< 828 <1 5<1 $/ ! 792 " 2?9, " 24?!8:&992!9,8 / "&99," 92" '25?( 92 ! The clock frequency generation for the S3C8238/C8235/F8235 by an external crystal can range from 1 MHz to 8 MHz. The maximum CPU clock frequency is 8 MHz (mask version is 10 MHz). The X and X pins connect the external oscillator or clock source to the on-chip clock circuit. The system clock circuit has the following components: -- External crystal or ceramic resonator oscillation source (or an external clock source) -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- System clock control register, CLKCON -- Oscillator control register, OSCCON and STOP control register, STPCON !" # " $ % &'() %)&% The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. -- In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters. Idle mode is released by a reset or by an external or internal interrupt. *+ ! + +, +. + "$"-./0 12 ')34 " " "$ "0 5 " !#"$% &' ("') &6+-, *3 * !+%! & ' &" The system clock control register, CLKCON, is located in the bank 0 of set 1, address D4H. It is read/write addressable and has the following functions: -- Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to f/8, f/2, or f/1. 7 4#&6+% '-899 " 5 : 0 ; , . &5 +3#7 < .% +3#7 < .% ')3 72= ..>"0 .>"$ .>" >"#3)33% , !+ &" $&- .$ & When a main oscillator is selected, users cannot stop operating of a main oscillator by handling the OSCCON register but sub oscillator can be stopped. If users intend to stop operating of a main oscillator users must use "STOP" instruction. When a sub oscillator is selected, users must do the contrary of the above case. In stop mode selected by the OSCCON register not by "STOP" instruction, users can release stop mode only by handling the OSCCON register not by interrupts. 4#+% 1,8995 7.9 " 5 : 0 ; , . &5 +3 7 = .> > +3 = .> + > = .> + > !! 3 !! ? 0;##",:0$%$0% 8!< ! 4 ) ! 4 ! 33 ? < ! 0; / &" 4#+% 1-8995 7.9 " 5 : 0 ; , . &5 = !) >' ....>@ 0( (&" During a power-on reset, the voltage at V goes to High level and the pin is forced to Low level. The signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C8238/C8235/F8235 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both V and are High level), the pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values In summary, the following sequence of events occurs during a reset operation: -- Interrupt is disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0-4 are set to input mode. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed. In normal (masked ROM) mode, the Test pin is tied to V. A reset enables access to the 16-Kbyte on-chip ROM. (The external interface is not automatically configured). To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON. Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined after a reset. -- A dash ("-") means that the bit is either not used or not mapped, but read 0 is the bit value. !"# $%#& $'#()*+ !"# $ , LCD control register LCD mode register Basic timer control register Clock Control register System flags register Register pointer 0 Register pointer 1 Stack pointer (high byte) Stack pointer (low byte) Instruction pointer (high byte) Instruction pointer (low byte) Interrupt request register Interrupt mask register System mode register Register page pointer -,)-". LCON LMOD BTCON CLKCON FLAGS RP0 RP1 SPH SPL IPH IPL IRQ IMR SYM PP **$## . 208 209 211 212 213 214 215 216 217 218 219 220 221 222 223 0 D0H D1H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH 1 0 0 0 0 x 1 1 x x x x 0 x 0 0 0 0 0 0 x 1 1 x x x x 0 x - 0 /" %# & $ 2 0 0 0 0 x 0 0 x x x x 0 x - 0 3 0 0 0 0 x 0 0 x x x x 0 x x 0 0 0 0 0 x 0 1 x x x x 0 x x 0 0 0 0 0 x - - x x x x 0 x x 0 0 0 0 0 0 - - x x x x 0 x 0 0 4 0 0 0 0 0 - - x x x x 0 x 0 0 Location D2H is not mapped 5/-(4!"# $%#& $'#()*+ !"# $ , Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 0 interrupt control register Port 0 interrupt pending register Port 3 interrupt control register Port 3 interrupt pending register Timer A/1 interrupt pending register Timer A control register Timer A counter register Timer A data register Timer B control register Timer B data register(high byte) Timer B data register(low byte) Key strobe data register Voltage level detector control register Watch timer control register Oscillator control register STOP control register Pattern generation control register Pattern generation data register AD converter control register AD converter data register(high byte) AD converter data register(low byte) AD interrupt register Carrier on/off control signal Basic timer data register Interrupt priority register -,)-". P0 P1 P2 P3 P4 P0INT P0PND P3INT P3PND TINTPND TACON TACNT TADATA TBCON TBDATAH TBDATAL KSDATA VLDCON WTCON OSCCON STPCON PGCON PGDATA ADCON ADDATAH ADDATAL ADINT REMCON BTCNT IPR **$## . 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 253 255 0 E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FDH FFH 1 0 0 0 - - 0 0 - - - 0 0 1 0 1 1 0 0 0 0 0 - 0 0 x 0 0 - 0 x 2 0 0 0 - - 0 0 - - - 0 0 1 0 1 1 0 0 0 0 0 - 0 0 x 0 0 - 0 x /" %# & $# 0 0 0 - - 0 0 - - - 0 0 1 0 1 1 0 0 0 0 0 - 0 0 x 0 0 - 0 x 3 0 0 0 - - 0 0 - - - 0 0 1 0 1 1 0 0 0 0 0 - 0 0 x 0 0 - 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 - 0 0 x 0 0 - 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 x 0 0 - 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 x x 0 - 0 x 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 x x 0 0 0 x Location FCH is factory use only Location FEH is not mapped 5/-(!"# $%#& $'#()*+ !"# $ , Port 0 control High register Port 0 control Low register Port 1 pull-up control register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control register Port 4 control register Key strobe control register -,)-". P0CONH P0CONL P1PUR P1CONH P1CONL P2CONH P2CONL P3CON P4CON KSCON **$## . 224 225 227 228 229 230 231 232 234 235 0 E0H E1H E3H E4H E5H E6H E7H E8H EAH EBH 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 /" %# & $# 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 Location E2H is not mapped. Location E9H is not mapped Locations ECH - EFH are not mapped Location F0H is factory use only. Timer 1 control register Timer 1 counter register(high byte) Timer 1 counter register(low byte) Timer 1 data register 1(high byte) Timer 1 data register 1(low byte) Timer 1 data register 2(high byte) Timer 1 data register 2(low byte) Timer 1 prescaler T1CON T1CNTH T1CNTL T1DATA1H T1DATA1L T1DATA2H T1DATA2L T1PS 241 242 243 244 245 246 247 248 F1H F2H F3H F4H F5H F6H F7H F8H 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Locations F9H - FFH are not mapped Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 A. All system functions stop when the clock "freezes," but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by interrupts. Do not use stop mode if you are using an external clock source because X input must be restricted internally to V to reduce current leakage. #"-! )# )6)* Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H). #"-!-0 $-- $$%6 )# )6)* External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode. The external interrupts in the S3C8238/C8235/F8235 interrupt structure that can be used to release Stop mode are: -- External interrupts P0.0-P0.7 (INT0-NT7) Please note the following conditions for Stop mode release: -- If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except $!"# $. -- If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. -- When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. -- The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. #"-!-"- $-- $$%6 )# )6)* Activate any enabled interrupt, causing stop mode to be released. Other things are same as using external interrupt. )7 )- $"- )# )6,)* There are two ways to enter into stop mode. -- Handling OSCCON register. -- Handling STPCON register then writing STOP instruction. (Keep the order) Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to `00B'. If interrupts are masked, a reset is the only way to release idle mode. 2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed. 0 The S3C8238/C8235/F8235 microcontroller has five bit-programmable I/O ports, P0-P4. The port 3 and port 4 are 4-bit ports and the others are 8-bit ports. This gives a total of 32 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3C8238/C8235/F8235 I/O port functions. 1-bit programmable I/O port. Schmitt trigger input or output mode selected by software; software assignable pull-up. P0.0-P0.7 can be used as inputs for external interrupts INT0-INT7 (with noise filter and interrupt control). 1-bit programmable I/O port. Normal input, AD input and output mode selected by software; for P1.0-P1.3, push-pull or open-drain output mode can be selected by software; software assignable pull-up. Alternatively P1.4-P1.7 can be used as PG0-PG3. 1-bit programmable I/O port. Normal input, open-drain and push-pull output with software assignable pull-up. Alternatively P2.0-P2.7 can be used as SEG12-SEG19. 1-bit programmable I/O port. Push-pull output and schmitt trigger input with mode selected by software. P3.0-P3.3 can alternately be used as KIN0-KIN3. 1-bit programmable I/O port. Push-pull output and normal input mode with software assignable pull-up. Alternatively P4 can be used asPG4-PG7. 1 2 3 4 !"##!$%&$! Table 9-2 gives you an overview of the register locations of all five S3C8238/C8235/F8235 I/O port data registers. Data registers for ports 0, 1, 2, 3, and 4 have the general format shown in Figure 9-1. "! ''( ! )' Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register *'+ P0 P1 P2 P3 P4 "+' 224 225 226 227 228 ,- E0H E1H E2H E3H E4H .+ Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 Set 1, Bank 0 !/ R/W R/W R/W R/W R/W !0 Port 0 is an 8-bit I/O Port that you can use two ways: -- General-purpose I/O -- External interrupt inputs for INT0-INT7 -- Alternative function Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0. 0 ! 10 ),20 ).3 Port 0 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 1: P0CONL (low byte, E1H) and P0CONH (high byte, E0H). When you select output mode, a push-pull circuit is configured. In input mode, three different selections are available: -- Schmitt trigger input with interrupt generation on falling signal edges. -- Schmitt trigger input with timer 1 capture signal. -- Schmitt trigger input with interrupt generation on falling/rising signal edges. 0&$44! 10&)20)"3 To process external interrupts at the port 0 pins, two additional control registers are provided: the port 0 interrupt enable register P0INT (E5H, set 1, bank 0) and the port 0 interrupt pending register P0PND (E6H, set 1, bank 0). The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P0PND register at regular intervals. When the interrupt enable bit of any port 0 pin is "1", a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P0PND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding P0PND bit. !" !# !$ !% !& !' ! ! !" !# !$ !% ()")* ()#)+ ()$),) ()%) !"!#- !")*()" (./012-1 /.)* ./3 (./01./3/.24 1 /. /3.//./ (./01)* ./34 !$!%- !#)+()# (./012-1 /.)+ ./ (./01./3/.24 1 /.)+ ./ /3.//./ /3.//./ !&!'- !$),)()$ (./012-1 /. (./01./3/.24 1 /. /3.//./ * 54/6 2),) !!- !%) ()% (./012-1 /. (./01./3/.24 1 /. /3.//./ * 54/6 2) 0,56( ! 10 ),3 7 !" !# !$ !% !& !' ! ! !& ()& !' ()' ! () ! () !"!#- !&()& (./012 /. 1 (./01./3/.2 /.4 1 (./012 /.-1 /3.//./ !$!%- !'()' (./012 /. 1 (./01./3/.2 /.4 1 (./012 /.-1 /3.//./ !&!'- !() (./012 /. 1 (./01./3/.2 /.4 1 (./012 /.-1 /3.//./ !!- !() (./012 /. 1 (./01./3/.2 /.4 1 (./012 /.-1 /3.//./ 0.6( ! 10 ).3 (/. () $ !" !# !$ !% !& !' ! ! ()" ()# ()$ ()% ()& ()' () () () 4 / 8 (/.1 - (/.- 0& ! 10&)3 (/.1 9 # !" !# !$ !% !& !' ! ! 9" 9# 9$ 9% 9& 9' 9 9 9 4 / 8 (/.:/ .1 .1 - 677 (/.:/ .1 7 0&4! 10)"3 ! Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0. P1.0-P1.7 can serve as inputs outputs (push pull or open-drain) or you can configure the following alternative functions: -- Low-byte pins (P1.0-P1.3): AD0-AD3 -- High-byte pins (P1.4-P1.7): AD4-AD7, COM4-COM7, PG0-PG3 ! 1 ),2 ).3 Port 1 has two 8-bit control registers: P1CONH for P1.4-P1.7 and P1CONL for P1.0-P1.3. A reset clears the P1CONH and P1CONL registers to "00H", configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull or open drain) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 1 control registers must also be enabled in the associated peripheral module. ! $! 18!3 Using the port 1 pull-up resistor enable register, P1PUR (E3H, set 1, bank 1), you can configure pull-up resistors to individual port 1 pins. % !" !# !$ !% !& !' ! ! !%*9% "; !$*9$ #; !#*9# $;' !"*9" %;& !"!#- !";&*9" % (./01 *9"65 ./80 ./44 /3.//./ %/./- * 54/6 8;&/./ !$!%- !#;'*9# $ (./01 *9#65 ./80 ./44 /3.//./ $/./- * 54/6 8;'/./ !&!'- !$;*9$ # (./01 *9$65 ./80 ./44 /3.//./ #/./- * 54/6 8;/./ !!- !%;*9% " (./01 *9%65 ./80 ./44 /3.//./ "/./- * 54/6 8;/./ //./0/-64./3/. 6/! ,56( ! 1 ),3 7 $ !" !# !$ !% !& !' ! ! !*9 !*9 !'*9' !&*9& !"!#- !&*9& (./01 *9& ./80 ./44 /3.//./ .31 /./ !$!%- !'*9' (./01 *9' ./80 ./44 /3.//./ .31 /./ !&!'- !*9 (./01 *9 ./80 ./44 /3.//./ .31 /./ !!- !*9 (./01 *9 ./80 ./44 /3.//./ .31 /./ //./0/-64./3/. 6/! 9 .6( ! 1 ).3 /3/. , & !" !# !$ !% !& !' ! ! !" !# !$ !% !& !' ! ! , 4 / 8 /3/.1 - /3/.- : ! 18!3 ! Port 2 is an 8-bit I/O port that can be used for general-purpose I/O and SEG12-SEG19. The pins are accessed directly by writing or reading the port 2 data register, P2 at location E2H in set 1, bank 0. To individually configure the port 2 pins P2.0-P2.7, you make bit-pair settings in two control registers located in set 1, bank 1: P2CONL (low byte, E7H) and P2CONH (high byte, E6H). ! 1 ),2 ).3 Two 8-bit control registers are used to configure port 2 pins: P2CONL (E7H, set 1, Bank 1) for pins P2.0-P2.3 and P2CONH (E6H, set 1, Bank 1) for pins P2.4-P2.7. Each byte contains four bit-pairs and each bit-pair configures one pin of port 2. ' ' # !" !# !$ !% !& !' ! ! '!%;#+) $ '!$;"+) # '!#;>+) " '!";=+) > !"!#- '!";=+) > (./01 (./01./3/. /3.//./;=+-+) >/./- .31 /./;=+-+) >/./- !$!%- '!#;>+) " (./01 (./01./3/. /3.//./;>+-+) "/./- .31 /./;>+-+) "/./- !&!'- '!$;"+) # (./01 (./01./3/. /3.//./;"+-+) #/./- .31 /./;"+-+) #/./- !!- '!%;#+) $ (./01 (./01./3/. /3.//./;#+-+) $/./- .31 /./;#+-+) $/./- ,56( ! 1 ),3 ' 7' " !" !# !$ !% !& !' ! ! '!;'+) '!;&+) ' '!';%+) & '!&;$+) % !"!#- '!&;$+) % (./01 (./01./3/. /3.//./;$+-+) %/./- .31 /./;$+-+) %/./- !$!%- '!';%+) & (./01 (./01./3/. /3.//./;%+-+) &/./- .31 /./;%+-+) &/./- !&!'- '!;&+) ' (./01 (./01./3/. /3.//./;&+-+) '/./- .31 /./;&+-+) '/./- !!- '!;'+) (./01 (./01./3/. /3.//./;'+-+) /./- .31 /./;'+-+) /./- .6( ! 1 ).3 ! Port 3 is an 4-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E3H in set 1, bank 0. P3.0-P3.3 can serve as inputs as push-pull outputs, or you can configure the following alternative functions: -- TACAP, TACK, TAOUT, TAPWM , Watch Timer, Buzzer output and KIN0-KIN3 inputs ! 1 )3 A reset clears the P3CON registers to "00H", configuring all pins to input mode. You use control registers settings to select input or output mode, and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 3 control registers must also be enabled in the associated peripheral module. & & > !" !# !$ !% !& !' ! ! &!)* )*,)+( &!)*++( &!')**+(' &!&,?+(& !"!#- &!&,?+(& (./012@ /. 6 0-/AA/./ /3.//./ * 5012+(&+ ./24 1 /. -/./ -+!"B./ 3 0.161/ 51./13/.1/ -/ !$!%- &!')**+(' @ (./012@ /.)** ./ /3.//./ * 5012+(' -/./ -+!"B./ 3 0.161/ 51./13/.1/ -/ !&!'- &!)*++( @ (./012@ /.)** ./ /3.//./ * 5012+( -/./ -+!"B./ 3 0.161/ 51./13/.1/ -/ !!- &!)* )*,)+( (./012@ /. )* )*,)/./ /3.//./ * 5012+( -/./ -+!"B./ 3 0.161/ 51./13/.1/ -/ 0 ! 1 )3 &(/. &() " !" !# !$ !% !& !' ! ! &!&+(& &!'+(' &!+( &!+( (/.-9 -6 @ (/.1 - (/.-24 1 (/.-2 1 /7/. & 501 ./+(3+(&/564 1 /.! & ! 1 &)3 &(/.1 &9 > !" !# !$ !% !& !' ! ! /1 1 8 +(& +(' +( +( /..1 7 .1 6 (/. .1 &4! 1 )"3 ! " !7 Port 4 is an 4-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E4H in set 1, bank 0. P4.0-P4.3 can serve as inputs (with or without pull-up), and output (open drain or push-pull). And they can serve as segment pins for LCD, and alternative function PG4PG7 outputs. 7 ! 17 )3 A reset clears the P4CON registers to "00H", configuring all pins to input mode. % % * !" !# !$ !% !& !' ! ! %!;';%+) = %!;';$+) %!';'';#+) %!&;'&;"+) ' !"!#- %!&;'&;"+) ' (./01 (./01./3/. /3.//./;'&+-+) '/./- * 54/6 2;"/./ !$!%- %!';'';#+) (./01 (./01./3/. /3.//./;''+-+) /./- * 54/6 2;#/./ !&!'- %!;';$+) (./01 (./01./3/. /3.//./;'+-+) /./- * 54/6 2;$/./ !!- %!;';%+) = (./01 (./01./3/. /3.//./;'+-+) =/./- * 54/6 2;%/./ 7 ! 17 )3 You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024 or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only) -- Basic timer control register, BTCON (set 1, D3H, read/write) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using register addressing mode. A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of f/4096. To disable the watchdog function, write the signature code '1010B' to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0. ! " # $ % & 3( ))* &&+)43( ,- 3 '-+5 )43( ,- '( )* &+ ,, + ('( - )* &+ ,, + .- / )* &&+,00$&1" &+,00&%$ &+,00%2 + -( !" ! # $ % &!'( ! You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. The MCU is reseted whenever a basic timer counter overflow occurs, During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occuring, To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. ""! !)"*! !+" ! You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. During stop mode, a power-on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. When a BTCNT.4 overflow occurs, normal CPU operation resumes. % 55 7 >&&0000> () ,00$&1" ,00 <= ,00&%$ ,00%2 & 8; - 268. - (6 ? =@ RESET 378 - . 4 6 . 378((- 3 9- ( ): '- )$ ,3) - ' , 4 ,"-$ The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, you can select one of them using the appropriate TACON setting: -- Interval timer mode (Toggle output at TAOUT pin) -- Capture input mode with a rising or falling edge trigger at the TACAP pin -- PWM mode (TAPWM) Timer A has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, or 64 ) with multiplexer -- External clock input pin ( TACK) -- 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA) -- I/O pins for capture input (TACAP) or PWM or match output (TAPWM, TAOUT) -- Timer A overflow interrupt (IRQ0, vector E0H) and match/capture interrupt (IRQ0, vector DEH) generation -- Timer A control register, TACON (set 1, bank0, EAH, read/write) !" # The timer A module can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/ capture interrupt (TAINT). TAOVF is interrupt level IRQ0, vector E0H. TAINT also belongs to interrupt level IRQ0, but is assigned the separate vector address, DEH. A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer A match/capture interrupt, TAINT pending condition is also cleared by hardware when it has been serviced. $!% The timer A module can generate an interrupt: the timer A match interrupt (TAINT). TAINT belongs to interrupt level IRQ0, and is assigned the separate vector address, DEH. When timer A measure interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware. In interval timer mode, a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register, TADATA. The match signal generates a timer A match interrupt (TAINT, vector DEH) and clears the counter. If, for example, you write the value 10H to TADATA and 0AH to TACON, the counter will increment until it reaches 10H. At this point, the TA interrupt request is generated, the counter value is reset, and counting resumes. %"&'"%!'" Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the TAPWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at FFH, and then continues incrementing from 00H. Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t * 256 . !'" In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TA data register. You can select rising or falling edges to trigger this operation. Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by setting the value of the timer A capture input selection bit in the port 3 control register, P3CON, (set 1, bank 1, E8H). When P3CONL.7.6 is 00, the TACAP input or normal input is selected. When P3CON.7.6 is set to 10, normal output is selected. Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into the TA data register. By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TACAP pin. ' () # You use the timer A control register, TACON, to -- Select the timer A operating mode (interval timer, capture mode and PWM mode) -- Select the timer A input clock frequency -- Clear the timer A counter, TACNT -- Enable the timer A overflow interrupt or timer A match/capture interrupt -- Clear timer A match/capture interrupt pending conditions TACON is located in set 1, Bank 0 at address EAH, and is read/write addressable using Register addressing mode. A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address E0H. When a timer A overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware. To enable the timer A match/capture interrupt (IRQ0, vector DEH), you must write TACON.1 to "1". To generate the exact time interval, you should write TACON.3 and .0, which cleared counter and interrupt pending bit. When interrupt service routine is served, the pending condition must be cleared by software by writing a `0' to the interrupt pending bit. ! "# "$ "% "& "' "( " " +,) ) ) - .011(& .011(%$ .011$& .1 ) )2 + 3 ) - .4 5 363 .+,3)+, 3 ), , 78) )), .+,3)+, 0 3 ), , 78) )), .9!378 ,+ 3)* ,+) )), ,3 )*)+, ,+ - - ./- ,+ . - ,+ 50 : ,+ - - ./- 50 : ,+ . - 50 : ,+ ), ) - .00) . *), when write * *), ) -"'*;<-), ) 3 3 ) 3,) =" *++,+- %* # .(/ )' "( "#<"$ 011(& 011(%$ 011$& 2 ! 6 > /, ; ;<-6+<, 3 = 50 : 9 3 49/" 78 "' ;<-+ 9 ! 6 > !)* " ! 6 > 9 3 49/" 4 ,00 6 9! "%"& / 3 ; /, "* 9!3)* ) ) ), " ("9 3 - )349/" "%"& 9?,+, *++,0- !%.%1 !*! The S3C8238/C8235/F8235 micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the carrier frequency of a remote controller signal. Timer B has two functions: -- As a normal interval timer, generating a timer B interrupt at programmed time intervals. -- To supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow interrupt. "$<"# "( 9?,+, " !" 011 011( 011& 011; ! 6 > 2 ;< /: , 6 30 : 68 !6> *- ) ,)) ) 9"&9! + 4 ,+ !6> "' 4"? 4 B 4 / := / *= "&<"% /, 4 )0 "%<"&@@*5 ,0*/ 33 *;<-), :* *+ 0*" 3* 0, 30 :)), *), *5 ,0*/ 33:**5 ,0*;<-), " :50* 1-:)),*5 ,0*/ 33:**5 ,0 *;<-), ",+,9!):5=,*59"<"AA 3 !"@@" *++,2- .!%.%1 !*! / ! "# "$ "% "& "' "( " " +,) ) ) - .011 .011( .011& .011; ,+ ) - .4 ,+ / , 30 : .4 ,+ /, 30 : .4 ,+ / 3/ , 30 : .4 5 3 ,+,0 +<0 + ) - .<88 :/ <*3 . + 3 +- .+ . ,+ - - ./- ,+ . - ,+ *++,3- .%* . # /*<= / ! "# "$ "% "& "' "( " " 7 ,88* / :<= / 8 ! "# "$ "% "& "' "( " " 7 ,88* *++,4- .* 00 ! / ! "# "$ "% "& "' "( " " ,3 = 00 ." .9! *++,5-!677%* )'' ) 8*& ORG VECTOR VECTOR ORG INITIAL: LD LD LD LD LD LD LD EI MAIN: * * * 0000h 0DEh,TAMC_INT 0E0h,TAOV_INT 0100h SYM,#00h IMR,#00000010b SPH,#00000000b SPL,#00000000b BTCON,#10100011b TADATA,#80h TACON,#01001010b ; Disable Global/Fast interrupt SYM ; Enable IRQ0 interrupt ; Set stack area ; Disable watch-dog ; Match interrupt enable ; 3.28 ms duration (10 MHz x'tal) MAIN ROUTINE * * * JR TAMC_INT: * * * T,MIAN Interrupt service routine * * * IRET TAOV_INT: .END )'' ) 8*& . ORG VECTOR ORG INITIAL: LD LD LD LD LD SB1 LD SB0 LD LD LD SYM,#00h IMR,#00000010b SPH,#00000000b SPL,#00000000b BTCON,#10100011b ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watch-dog 0000h 0E2h,TBUN_INT 0100h P0CONH,#00000011b TBDATAH,#80h TBDATAL,#80h TBCON,#11001110b ; Enable TBPWM output ; Enable interrupt ; Duration 202 s (10 MHz x'tal) EI MAIN: * * * MAIN ROUTINE * * * JR TBUN_INT: * * * T,MIAN Interrupt service routine * * * IRET .END The 16-bit timer 1 is an 16-bit general-purpose timer/counter. Timer 1 has three operating modes, one of which you select using the appropriate T1CON setting. -- Interval timer mode (Toggle output at T1OUT pin) -- Capture input mode with a rising or falling edge trigger at the T1CAP pin Timer 1 has the following functional components: -- Clock frequency divider (fxx divided by 64, 8 or 1) with multiplexer -- External clock input pin (T1CK, TBUF) -- A 16-bit counter (T1CNTH/L), a 16-bit comparator, and two 16-bit reference data register (T1DATA1, T1DATA2) -- I/O pins for capture input (T1CAP), or match output (T1OUT) -- Timer 1 overflow interrupt (IRQ2, vector E6H) and match/capture interrupt (IRQ2, vector E4H) generation -- Timer 1 control register, T1CON (set 1, F1H, Bank 1, read/write) !" # $ The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1 match/capture interrupt (T1INT). T1OVF is interrupt level IRQ2, vector E6H. T1INT also belongs to interrupt level IRQ2, but is assigned the separate vector address, E4H. A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. A timer 1 match/capture interrupt, T1INT pending condition is also cleared by hardware when it has been serviced. %!&'"!($ The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT). T1INT belongs to interrupt level IRQ2, and is assigned the separate vector address, E4H. In interval timer mode, a match signal is generated and T1OUT is toggled when the counter value is identical to the value written to the T1 reference data register, T1DATA1H/L. The match signal generates a timer 1 match interrupt (T1INT, vector E4H) and clears the counter. !'" In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the T1 data register (T1DATA1H/L for rising edge, T1DATA2H/L for falling edge). You can select rising or falling edges to trigger this operation. Timer 1 also gives you capture input source, the signal edge at the T1CAP pin. You select the capture input by setting the value of the timer 1 capture input selection bit in the port 1 control register high, P1CONH, (set 1 bank 0, E0H). When P1CONH.7-.6 is 00 or 11, the T1CAP input is selected . Both kinds of timer 1 interrupts (T1OVF, T1INT) can be used in capture mode, the timer 1 overflow interrupt is generated whenever a counter overflow occurs, the timer 1 capture interrupt is generated whenever the counter value is loaded into the T1 data register. By reading the captured data value in T1DATAH/L, and assuming a specific value for the timer 1 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin. ' ) * $ You use the timer 1 control register, T1CON, to -- Select the timer 1 operating mode (interval timer, capture mode) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, T1CNTH/L -- Enable the timer 1 overflow interrupt or timer 1 match/capture interrupt -- Clear timer 1 match/capture interrupt pending conditions T1CON is located in set 1 and Bank 1 at address F1H, and is read/write addressable using Register addressing mode. A reset clears T1CON to `00H'. This sets timer 1 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1 interrupts. To disable the counter operation, please set T1CON.7-.5 to 111B. You can clear the timer 1 counter at any time during normal operation by writing a "1" to T1CON.3. The timer 1 overflow interrupt (T1OVF) is interrupt level IRQ2 and has the vector address E6H. To detect a match/capture or overflow interrupt pending condition when T1INT or T1OVF is disabled, the application program should poll the pending bit TINTPND register, bank 0 E9H. When a "1" is detected, a timer 1 match/capture or overflow interrupt is pending. When the sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the interrupt pending bit. If interrupt(match/capture or overflow) are enabled, the pending bit is cleared automatically by hardware. ! "# $% '!" ( ) * + , . &!" # 2 ...3055$ ..3055$6 ..3055$)+ .37 .53"8 53 /01 2 .3 /01 34 /01 :$ 2 .3 34 ; 2 .300 3;< 2 ..3/ .3 0 9 .3 9 3 : 9 +,-& +$ .)/0* 0' (<* 055$ 055$6 055$)+ 7 "8 9 . /01 +< )< +, 8 1 :: +< ! :+< >:$ >- ' 8 = !&1+< ; ' 8 = "00 +, ? ;;)< ;;-)< +,-!&.&1!+! !" # $% & ' (#)# * +#)#& , % '$ *$#- . / (+0, * ( *$- *$ $ / #1#( +0,* ( $ $ ' !"23#)# *# # *# # #)#& *# #*# # ' !"23#)# * *# # *# # #)#& *# #*# # # $% * #)# # ## & # # # #*#)# ;;;; +<,3. . .. .(<)3.. ! ;; ;;+<,3. . .. .(<)3 ! * 0''* 2+( ORG VECTOR ORG INITIAL: LD LD LD LD LD SB1 LD LDW LD EI MAIN: * * * 0000h 0E4h,T1MC_INT 0100h SYM,#00h IMR,#00000100b SPH,#00000000b SPL,#00000000b BTCON,#10100011b ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watch-dog T1CON,#01000110b T1DATA1H,#0F0h T1PS,#00h ; Enable interrupt ; Duration 1.536 ms (10 MHz x'tal) MAIN ROUTINE * * * JR TBUN_INT: * * * T,MIAN Interrupt service routine * * * IRET .END Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 and bit 6 of the watch timer mode register, WTCON.1 and .6, to "1". After the watch timer starts and elapses a time, the watch timer interrupt is automatically set to "1", and interrupt requests commence in 3.9ms, 0.25 s, 0.5s or 1.0s intervals. The watch timer can generate a steady 0.5kHz, 1kHz, 2 kHz or 4 kHz signal to the BUZZER output. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. The watch timer supplies the clock frequency for the LCD controller (f ). Therefore, . -- Real-Time and Watch-Time Measurement -- Using a Main System or Subsystem Clock Source -- Clock Source Generation for LCD Controller -- Buzzer Output Frequency Generator -- Timing Tests in High-Speed Mode !"# $%& '( RESET )* )+ ), )- ). )( )/ )0 "0" "0" "0" "0" "0" "0" "0" "0" /.1/) 2 # &$"/340'(% 3 WTCON.7 WTCON.6 WTCON .5 - .4 0 0 1 1 WTCON .3 - .2 0 0 1 1 WTCON.1 WTCON.0 0 1 0 1 56 0 1 0 1 0 1 0 1 0 1 0 1 '6 Select (fxx/128 ) as the watch timer clock Select subsystem clock as watch timer clock Disable watch timer interrupt Enable watch timer interrupt 0.5 kHz buzzer (BUZ) signal output 1 kHz buzzer (BUZ) signal output 2 kHz buzzer (BUZ) signal output 4 kHz buzzer (BUZ) signal output Set watch timer interrupt to 1.0S. Set watch timer interrupt to 0.5S. Set watch timer interrupt to 0.25S. Set watch timer interrupt to 3.91mS. Disable watch timer; clear frequency dividing circuits Enable watch timer interrupt is not pending, clear pending bit when write interrupt is pending F2H 7! * ' 1 ( +7 %'&*$,-. %1&($,-. %(&$,-. %4&'$,-. !#6 6! 3 #!$ !#6 134$,869!/ :"; 6! &$,. &'),. &'),. (4 !"!#!$%"&'()*+,-. / 0 #!$&1234,-. %!506 '26/.1/) 62 8! ORG !897 2 0000h 0E8h,WT_INT 0100h VECTOR ORG INITIAL: LD LD LD LD LD LD EI MAIN: * * * SYM,#00h IMR,#00100000b SPH,#00000000b SPL,#00000000b BTCON,#10100011b WTCON,#11001110b ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watch-dog ; 0.5 KHz buzzer/3.91ms duration interrupt (10 MHz x'tal) MAIN ROUTINE * * * JR TBUN_INT: * * * T,MIAN AND IRET .END WTCON,#11111110b ; pending clear The S3F8325 micro-controller can directly drive an up-to-24-digit (24-segment) LCD panel. The LCD module has the following components: -- LCD controller/driver -- Display RAM (00H-17H) for storing display data in page 2 -- 24 segment output pins (SEG0 - SEG23) -- 8 common output pins (COM0 - COM7) -- 4 LCD operating power supply pins (V-V) Bit settings in the LCD mode register, LMOD, determine the LCD frame frequency, duty and bias, and the segment pins used for display output. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during stop and idle modes. The LCD control register LCON turns the LCD display on and off and switches current to the charge-pump circuits for the display. LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control. #$ #$% #$& #$ #$ #$ #$ #$ #$ #$% #$& #$ #$ #$ #$ #$ #$ #$% #$& #$ #$ #$ #$ #$ !" ) !" '( !" +(' , *' RAM addresses 00H-17H of page 2 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG23 using a direct memory access (DMA) method that is synchronized with the fsignal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use. # # -+ -+ -+% -+% -+ -+ -+ -+ %# # -+ -+ -+% -+% % -+ -+ -+ -+ !"#$% $&$ ' $&()*+ ," " ' $&($% $&- LCON.7-.5 000 001 010 011 100 101 110 111 LCON.4 LCON.3-.2 LCD dot on/off control bit LCON.1-.0 Not used 00 01 1x 00 01 1x Off signal On signal Normal display Internal CAP bias; display off (Low signal output through COM/SEG) Booster Off Internal CAP bias; display on (Valid signal output through COM/SEG) External resistor bias; Booster Off; display on (Valid signal output through COM/SEG) 0.90V (Booster reference voltage ) 0.95V 1.00V 1.05V 1.10V 1.15V 1.20V 1.25V ! ! "#$ $' $( The LCD mode control register LMOD is mapped to RAM addresses D1H. LMOD controls these LCD functions: -- Duty and bias selection (LMOD.1-LMOD.0) -- LCDCK clock frequency selection (LMOD.3-LMOD.2) The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This is also referred to as the 'frame frequency.' Since LCDCK is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD and LCON register values to logic zero. This produces the following LCD control settings: -- Display is turned off -- LCDCK frequency is the watch timer clock (fw)/2 = 256 Hz The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. The LCD output voltage level is supplied by the voltage booster. ," . $- LMOD.7 LMOD.6 LMOD.5 LMOD.4 0 1 0 1 0 1 0 1 SEG20 - SEG23 output disable SEG20 - SEG23 output enable SEG16 - SEG19 output disable SEG16 - SEG19 output enable SEG12 - SEG15 output disable SEG12 - SEG15 output enable COM4 - COM7 output disable COM4 - COM7 output enable ! ," /#. "0"' 1( $)' 1( 00 : (fw) / 2 01 : (fw) / 2 10 : (fw) / 2 11 : (fw) / 2 ' $*( 256 512 1024 2048 2#' $* $( 23#' $* $4( 64 128 256 512 32 64 128 256 ./'012 # / 3 $ $% $& $ $ $ $ $ 474 *8 .0*8068= 474.0*8 474*8 %)474 *8 .0*8068= 474.0*8 474*8 &474 *8 .0*8068= 474.0*8 474*8 $$ $$ 45*.*006.07*5 .45 8*0 .45 8*0 9*6 66:1;2068 < < < < 474 *8 .0*8068= 474.0*8 474*8 . " 15$-$6$ The LCD segment output pins(SEG12-SEG23) can also output key strobe signal for key scan and KIN0-KIN3 pins check key-press. When SEG12-SEG23 are set as key strobe output, selected key strobe is output pin by pin continuously with selected interval and duration. When KIN# pins are set as an alternative mode, KIN# pins status is high impedance normally, but when key strobe is output through SEG# pins, KIN# pins status become pull-up enable input mode. To decide which SEG# pin output key strobe you should check P2 and P4 data register. If all SEG12-SEG23 are used as key strobe output, KSDATA data register are used as one 12-bit data register. If SEG16-SEG23 are used as key strobe output, KSDATA data register constains one number between 5 and 12. If SEG20-SEG23 are used as key strobe output, KSDATA data register constains one number between 9 and 12. KSDATA data register value is not changed until next strobe occurs. To decide which KIN# pin receive key strobe you should check P3PND register in interrupt routine. So, check KSDATA data register and P3PND register and you will get the key-press information. ;58/'01;,2 # *: / 3 $ $% $& $ $ $ $ $ ;508*88 ;508474.0*8 ;508474*8 ,40.? & ;508474706 A$A$ A$A$*.A$A$ 9 A$A$*.A$A$ - *8<080*.' 1056?40*(@4652 (06166:2 (061%66:2 (061)%66:2 (061 66:2 8.4* &4061$&66:2 %406166:2 >9>(*0.>6*$ 71#, " $ %&#' (# !# )) "#$ $ !(## )*+ ,- . " $ $ / #(# !)&! ,- / .! !& (# !)&! " $ 88$ The LCD display is turned on only when the voltage difference between the common and segment signals is greater than V. The LCD display is turned off when the difference between the common and segment signal voltages is less than V The turn-on voltage, + V or - V, is generated only when both signals are the selected signals of the bias. Table 14-7 shows LCD drive voltages for static mode, 1/3 bias, and 1/4 bias. ," 98"8" ':" - ( 6;!!"# V V V V V . V - - - 0V 2- - V 2/3 V 1/3 V 0V 2- V 3/4 V 2/4 V 1/4 V 0V &+0# #! 0"&!'& "$& '# "&+0'&1"$ 2 $& The 24 LCD segment signal pins are connected to corresponding display RAM locations at 00H-17H. Bits 0-7 of the display RAM are synchronized with the common signal output pins COM0, . . . . , and COM7. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. Each bias has select and no-select signals. 6 6: B*( ,6 <"2& "- " !"#. 6 B*( 6: ,6 4"2& "- " 2#)2- !"#. 6 B*( 6: ,6 3"2& "- " 23#)2- !"#. $&66: 4866: % #C ;508 66: A447*8 ;5746?6: ;574*8 A447*8 ;5746?6: ;574*8 =1#! >0/1#,$ B*( 6: 1A$2 +08 1.4*2 008;+ 008 ;+ + * 1A$2 .08;+ .08;+ 1A$2 ?08;+ 3??747408 ?07(40(**?'?0*40 *?4'?4740?'?$ *:!"?1#,.;>2#$! /2 *$3) " )$4)$ " !' ,$5 (.'&2 011 !6 ! $,. &%&% B/ B*( $9 $9 $%9% $9 " # $ ".@9 :!"23#)2- !"#. ! ! " # $ % & B/ B*( $9 $9 $9 $9 " # $ ! " # $ "! " .@9 :!"2#)2- !"#. " # $ "! " " "#! " # $ 8$ 8&+$ -#8"- For run the voltage booster -- Make enable the watch timer for f -- Set LCON.1-.0 to "01" for make enable voltage booster -- Recommendable capacitance value is 0.1 uF (CA/B, C1, C2, C3, C4) -#8"9. ':""#( For make external voltage dividing resistors -- Set LCON.1-.0 to "1x" for make disable voltage booster -- Make floating the CA and CB pin -- Recommendable R = 100 Kohm *01*&2 *01&*&2 / / / 9/ / / / *01*&2 *61&*&2 / / / / / / 84766A8*0 6?*7% *'80$ 8"9. 6$&6A ORG INITIAL: LD LD LD LD LD LD SB1 LD LD LD LD SB0 LD LD LD LD LCD_CLR LD LD DJNZ LD LD EI 100h > !"# SYM,#00h IMR,#00000000b BTCON,#10100001b CLKCON,#00011000b SPL,#0 SPH,#0 ; ; ; ; ; Disable Global/Fast interrupt Enable IRQ7 interrupt Disable Watchdog Select non-divided oscillator frequency Set SPL P1CONH,#10101010b P2CONH,#10101010b P2CONL,#10101010b P4CON,#10101010b ; ; ; ; Enable COM signal output Enable SEG16-SEG19 Enable SEG12-SEG15 Enable SEG20-SEG23 WTCON,#11000010b LCON,#11101001b LMOD,#11111100b ; LCD RAM clear routine........area: page 00h-17h R0,#17h PP,#20h @R0,#0 R0,LCD_CLR R0,#0 PP,#00h 6$&6A MAIN: LDW LD LDC DSP_LOOP: LD LD LD LD INC INCW IDC CP JP JP DSP_DAT: DB DB .END > !"#' .( << MAIN ROUTINE >> RR4,#0 R2,#0 R3,#DSP_DAT[RR4] R6,R2 PP,#20h @R6,R3 PP,#00 R2 RR4 R3,#DSP_DAT[RR4] R2,#17h ULE,DSP_LOOP MAIN 0,26h,49h,49h,32h,7Fh,8h,34h,43h,0,41h 7Fh,41h,0h,0h,7Fh,41h,41h,22h,1Ch,0,0,0,0,0,0 6!A ORG VECTOR ORG INITIAL: LD LD LD LD LD SB1 LD LD LD LD LD SB0 LD LD LD LD SB1 LD SB0 LD LCD_CLR: LD LD DJNZ LD LD CLR CLR CLR EI > 1#,. !"# 0000h 0FEh,KEY_INT 0100h SYM,#00h IMR,#10000000b SPH,#00000000b SPL,#00000000b BTCON,#10100011b P1CONH,#10101010b P2CONH,#10101010b P2CONL,#10101010b P4CON,#10101010b P3CON,#11111111b P3INT,#10101010b WTCON,#10001110b LCON,#01001101b LMOD,#11111000b KSCON,#10011111b ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watchdog ; ; ; ; ; ; ; ; ; Enable COM signal output Enable SEG signal output Enable SEG signal output Enable SEG signal output Enable Key strobe input Key input falling edge int. Clock generation for LCD display CAP bias, Enable LCD display 1/8duty & 1/4bias ; All ports are used as key strobe ; LCD RAM clear routine.... area : page2 00h-17h R0,#17h PP,#20h @R0,#0 R0,LCD_CLR @R0,#0 PP,#00h R0 R1 R6 6!A MAIN: NOP NOP NOP CLR CLR LD DSP_LOOP: LD ADD LDC LD LD LD INC INC CP JP JR DSP_DAT DB DB DB DB > 1#,. !"#' .( R6 R1 R4,#0 R5,R0 R5,R1 R3,#DSP_DAT[RR4] PP,#20H @R6,R3 PP,#00 R1 R6 R1,#24 ULT,DSP_LOOP T,MAIN 080h,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21 22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39 40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59 60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80 6!A KEY_INT: PUSH LD LD AND TM JP TM JP TM JP JP KEY_INT_KIN0: ADD JP KEY_INT_KIN1: ADD JP KEY_INT_KIN2: ADD JP KEY_INT_KIN3: ADD JP WHAT_KEY: LD POP IRET .END > 1#,. !"#' .( PP PP,#00H R0,KSDATA R0,#00001111b P3PND,#00000001b NZ,KEY_INT_KIN0 P3PND,#00000010b NZ,KEY_INT_KIN1 P3PND,#00000100b NZ,KEY_INT_KIN2 KEY_INT_KIN3 ; Mask high 4-bit of ksdata ; Check KIN0 ; Check KIN1 ; Check KIN2 R0,#0 WHAT_KEY R0,#12 WHAT_KEY R0,#24 WHAT_KEY R0,#36 WHAT_KEY P3PND,#00b PP ; pending clear The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the AV and AV values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- AD interrupt register(ADINT) -- Eight multiplexed analog data input pins (AD0 - AD7) , alternately digital data I/O port -- 10-bit A/D conversion data output register (ADDATAH/L) -- AV and AV pins, AV is internally connected to V To initiate an analog-to-digital conversion procedure, at the first you must set port control register(P1CONH/L) for AD analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.6 to select one of the eight analog input pins (AD0-7) and set the conversion start or enable bit, ADCON.0. The readwrite ADCON register is located in set 1, bank 1, at address F7H. The unused pin can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6 - 4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADINT.0, the end-of-conversion(EOC) bit or pending bit is automatically set to 1 and the result is dumped into the ADDATAH/L register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. !". You must use STOP or IDLE mode after ADC operation is finished. #$%&' The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When Fxx/8 is selected for conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10 bits + set-up time = 50 clocks, 50 clock x 1us = 50 us at 1 MHz !"#$%%#%%'%(!#) The A/D converter control register, ADCON, is located at address F7H in set 1, bank 0. It has three functions: -- Analog input pin selection ( bits 4, 5, and 6 ) -- ADC interrupt enable ( bit 3) -- A/D operation start or enable ( bit 0 ) -- A/D conversion speed selection (bit 1,2) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (ADC0-ADC7) can be selected dynamically by manipulating the ADCON.4-6 bits. And the pins not used for analog input can be used for normal I/O function. ! " "# "$ "% "& "' " " () *+ 010 *-. "#"$"% 010 ' & % $ # ,- -. /- 0 / 0 12* * *-. "'" * 6 344# 3445 344% 344 10- -. /- 10 /,- 10 * +,-+.!"# #% (!#) 7 10 78 ! " "# "$ "% "& "' " " 19 7 1009- , / 1009: 9 0 = Clear pending bit (When write) /7 1009: 9 * +,-/.!"# % (!) :)8 5 9) ) ! " "# "$ "% "& "' " " ()8 ; 9) ) ! 4 4 4 4 4 4 " " * +,-0.!"# % (!!!1") %!%*%#$!'$ In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AV to AV (usually, AV = V). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AV. "%2" *0103:9 "'2" * * 878" , 7 @# "& 701< 2 <"2<" ! 1 0 4 " ,- 2 ? >0 1** 00 4> * 2- 1 99 " - 2- = = 1 5; 8 * +,-2.!"# * 3 45 !# ORG VECTOR ORG INITIAL: LD LD LD LD LD SB1 LD LD SB0 LD LD EI MAIN: * * * 0000h 0FAh,ADC_INT 0100h SYM,#00h IMR,#01000000b SPH,#00000000b SPL,#00000000b BTCON,#10100011b ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watch-dog P1CONH,#01010101b P1CONL,#01010101b ; ADC input ; ADC input ADCON,#00001001b R4,#0 ; Enable ADC interrupt MAIN ROUTINE * * * JR TBUN_INT: * * * * * * T,MIAN ; Hardware pending clear OR IRET .END ADCON,#00000001b ; Resume conversion 45 !#& % ORG ORG INITIAL: LD LD LD LD LD SB1 LD LD SB0 LD LD EI MAIN: NOP OR NOP NOP NOP AD_LOOP: TM JP LD LD NOP NOP NOP JR .END T,MAIN ADINT,#00000001b Z,AD_LOOP ADINT,#0 R0,ADDATAH ADCON,#00000001b SYM,#00h IMR,#01000000b SPH,#00000000b SPL,#00000000b BTCON,#10100011b 0000h 0100h ; Disable Global/Fast interrupt ; Enable IRQ0 interrupt ; Set stack area ; Disable Watch-dog P1CONH,#01010101b P1CONL,#01010101b ; ADC input ; ADC input ADCON,#00000000b R4,#0 ; Disable ADC interrupt ; Conversion start ; Check EOC ; Pending clear by software This voltage booster works for the power control of LCD: generates 4 x V(V), 3 x V(V), 2 x V(V), 1 x V(V). This voltage booster allows low voltage operation of LCD display with high quality. This voltage booster circuit provides constant LCD contrast level even though battery power supply was lowered. This voltage booster include voltage regulator, and voltage charge/pump circuit. The voltage booster has built for driving the LCD. The voltage booster provides the capability of directly connecting an LCD panel to the MCU without having to separately generate and supply the higher voltages required by the LCD panel. The voltage booster operates on an internally generated and regulated LCD system voltage and generates a doubled , a tripled and a four-fold voltage levels to supply the LCD drive circuit. External capacitor are required to complete the power supply circuits. The Vdd power line is regulated to get the V(V) level, which become a base level for voltage boosting. Then a doubled ,a tripled and a four-fold voltage will be made by capacitor charge and pump circuit. # #$ %&' %&' !" ()**+**,*)-**.-/*0)*.*, ))-**,*,*)**+**,*.- *0)*.*,*0)- !" Supply Voltage Operating Temperature Range Storage Temperature Range #$ V T T -0.3 - 6.5 -40 - +85 -65 - +150 % V C C & (T= 25 C, V = 2.0 V to 5.5 V, V = 0 V) Operating Voltage Regulated Voltage Booster Voltage #$ V V V V V Connect 1 M load between V and V Connect 1 M load between V and V Connect 1 M load between V and V Connect 1 M load between V and V ' ! 2.0 0.85 2V x 0.9 3V x 0.9 4V x 0.9 $ - 1.05 - - - ! 5.5 1.30 2V x 1.1 3V x 1.1 4V x 1.1 % V The S3C8238/C8235/F8235 micro-controller has a built-in VLD(Voltage Level Detector) circuit which allows detection of power voltage drop through software. Turning the VLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during VLD operation. It is recommended that the VLD operation should be kept OFF unless it is necessary. Also the VLD criteria voltage can be set by the software. The criteria voltage can be set by matching to one of the 3 kinds of voltage 2.4V, 3.3V or 4.5V (VDD reference voltage). The VLD block works only when VLDCON.2 is set. If VDD level is lower than the reference voltage selected with VLDCON.1-.0, VLDCON.3 will be set. If VDD level is higher, VLDCON.3 will be cleared. Please do not operate the VLD block for minimize power current consumption. # $# % &'()(* +(,.)* / 0 )* ! !! "! 1 # # ) # # )! ! "#$% % % %"%"" %$&'"% The bit 2 of VLDCON controls to run or disable the operation of Voltage level detector. Basically this V is set as 2.4 V by system reset and it can be changed in 3 kinds voltages by selecting Voltage Level Detector Control register(VLDCON). When you write 2 bit data value to VLDCON, an established resistor string is selected and the V is fixed in accordance with this resistor. Table 17-1 shows specific V of 3 levels. # &'()(* +(,-(6' .)* / 0 )* 7 #9 8 * *2321 : , 4! # 5' !( ") ( ! * 00 01 10 11 2.4 V Not used 3.3 V 4.5 V ") + ! (T = 25 C) , Operating Voltage Detection Voltage '-) V V VLDCON.1.0 = 00b VLDCON.1.0 = 01b VLDCON.1.0 = 10b VLDCON.1.0 = 11b Current consumption I VLD on V = 5.5 V V = 3.0 V V = 2.0 V Hysteresis Voltage (Slew Rate of VLD) V VLDCON.1.0 = 00b VLDCON.1.0 = 11b - 2.9 4.1 - ( . 1.5 2.0 "-/ - 2.4 Not used 3.3 4.5 10 5 4 10 3.7 4.9 20 10 8 100 mV uA .0 5.5 2.8 1 V ,"/21+ ! ORG ORG INITIAL: SB0 LD LD LD LD LD LD LD EI MAIN: NOP NOP TM JP NOP NOP JR LOW_VDD: * * * 0000h 0100h Disable Global/Fast interrupt SYM Enable IRQ0 interrupt High byte of stack pointer SPH Low byte of stack pointer SPL Disable Watch-dog Non-divided SYM,#00h IMR,#00h SPH,#00h SPL,#00h BTCON,#10100011b CLKCON,#00011000b VLDCON,#00000100b ; ; ; ; ; ; ; Set 2.4 V VLDCON,#00001000b NZ,LOW_VDD ; If V is lower than the reference voltage ; VLDCON.3 bit is set T,NAIN JR .END T,MAIN You can output up to 8-bit through P1.4-P1.7 and P4.0-P4.3 by tracing the following sequence. First of all, you have to change the PGDATA into what you want to output. And then you have to set the PGCON to enable the pattern generation module and select the triggering signal. From now, bits of PGDATA are on the P1.4-P1.7 and P4.0-P4.3 whenever the selected triggering signal happens. ! *+,( ) -./!%!"0!,&' *%" 1 . 2 + 4+3 4 4 4"+$ 44 %&'4+ "2# +3 # 3 "#$$ #%&'() ! (%!"0!-1/) 1 . 2 "$$ 1 . 2 2 1 . %&' 4 4 4"+$ 44 "#$% %%&'() ORG ORG INITIAL: SB0 LD LD LD LD LD LD SB1 LD LD SB0 EI MAIN: NOP NOP OR NOP NOP JR .END T,NAIN PGCON,#00001000b ; Triggering then pattern data are output SYM,#00h IMR,#00h SPH,#00h SPL,#00h BTCON,#10100011b CLKCON,#00011000b P1CONH,#11111111b P4CON,#11111111b ; ; ; ; ; ; Disable Global/Fast interrupt SYM Enable IRQ0 interrupt High byte of stack pointer SPH Low byte of stack pointer SPL Disable Watch-dog Non-divided 0000h 0100h ; Enable PG output ; Enable PG output In this chapter, S3C8238/C8235 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- Input/output capacitance -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Data retention supply voltage in stop mode -- A/D converter electrical characteristics (T= 25 C) Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature V V V I I T T One I/O pin active All I/O pins active One I/O pin active Total pin current for port - 0.3 to +6.5 - 0.3 to V+ 0.3 - 0.3 to V + 0.3 - 18 - 60 +30 +100 - 40 to + 85 - 65 to + 150 C mA V !!"! ! (T= -40C to + 85 C, V = 2.0 V to 5.5 V) Operating voltage V V V Input low voltage V V f = 10 MHz f = 4 MHz Input high voltage All input pins except V XXT All input pins except V XXT 2.7 2.0 0.8 V V-0.1 - 0.2 V 0.1 # - 5.5 5.5 V V !!"! ! $ % (T= -40C to + 85C, V = 2.0 V to 5.5 V) Output high voltage V V V Output low voltage V V V Input high leakage current I I Input low leakage current I I Output high leakage current Output low leakage current Oscillator feed back resistors Pull-up resistor I I R R R COM output voltage deviation SEG output voltage deviation V V= 2.4 V; I = -4 mA Port 0.4 only V= 5 V; I = -4 mA Port 3 V= 5 V; I = -1 mA All output pins except P0.4,P3 V = 2.4 V; I = 12 mA P0.4 only V = 5 V; I = 15 mA P3 V = 5 V; I = 4 mA All output pins except P0.4,P3 V = V All input pins except I V = VXXT V= 0 V All input pins except I V= 0 V, X XT V = V All I/O pins and Output pins V = 0 V All I/O pins and Output pins V= 5.0 V T= 25 C X= V, X = 0 V V= 0 V; V= 5 V 10 % Port 0,1,2,4 T = 25C V= 0 V; V= 5 V 10% T=25 C, only V = V = 4 V (V -COMi) IO = 15 p-A (i = 0-3) V = V = 4 V (V -SEGi) IO = 15 p-A (i = 0-23) - - 800 25 110 - - - 1000 50 210 60 - - - - V- 0.7 V- 1.0 V - 1.0 # V- 0.3 - - 0.3 0.4 0.4 - - - - 0.5 2.0 2.0 3 20 -3 -20 3 -3 1200 100 310 200 mV k A V V - 60 200 !!"! ! $ !% (T= -40 C to + 85 C, V = 2.0 V to 5.5 V) Supply current I V= 5 V 10 % 10 MHz crystal oscillator 4 MHz crystal oscillator V= 3 V 10 % 10 MHz crystal oscillator 4 MHz crystal oscillator I Idle mode: V = 5 V 10 % 10 MHz crystal oscillator 4 MHz crystal oscillator Idle mode: V = 3 V 10 % 10 MHz crystal oscillator 4 MHz crystal oscillator I Sub operating: main-osc stop V= 3 V 10 % 32768 Hz crystal oscillator Sub idle mode: main osc stop V= 3 V 10 % 32768 Hz crystal oscillator Main stop mode : sub-osc stop V= 5 V 10 % V= 3 V 10 % - # 12 4 3 1 3 1.5 1.2 1.0 40 25 10 8 5 10 4 3 2.0 80 A mA I 7 14 I 1 0.5 3 2 ! " #$ % $ % &'( $ ) ) * $ % +( $ , ) "(++( - # &(. / # 0$ 1 "2 & !!"! ! (T= -40C to +85C, V = 2.0 V to 5.5 V) Interrupt input high, low width (P0.0-P0.7) input low width t, t t P0.0-P0.7, V = 5 V 200 # - - ns V = 5 V 1.5 - - S 3 % ) ) ' (#) (# $ *% RESET ' (#) + (#,-##!! (T= -40C to +85C, V=0 V ) Input capacitance Output capacitance I/O capacitance C C C f = 1 MHz; unmeasured pins are returned to V - # - 10 pF . ##/ # (T = -40C to + 85C) Data retention supply voltage Data retention supply current V I V= 2 V 2 - # - - 5.5 3 V A # ! " RESET $ %&'('() '& # ( # $ %&'('*+ '+ # $% ((# ! " # ,(('-()./'0,'1 '. # $ % ((# ! " 0 , 1 !!"! ! (T= - 40C to +85 C, V = 2.0 V to 5.5 V, V = 0 V) Resolution Total accuracy Integral Linearity Error ILE DLE EOT EOB T V R AV AV I I 10-bit resolution 50 x fxx/4, fxx = 10MHz - - - - AV = V = 5V AV = V = 5V AV = V = 3V AV = V = 5V When Power Down mode V = 5.12 V AV = 5.12V AV = 0 V CPU clock = 10 MHz - - - - - - 20 AV 2 2.5 V - - # 10 - - - 1 0.5 - - 1000 - - - 1 0.5 100 - 3 2 1 3 2 - AV - V V +0.3 10 3 1.5 500 nA A mA S V M V bit LSB Differential Linearity Error Offset Error of Top Offset Error of Bottom Conversion time Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current 4') 4 5 # ) " 6 ) " 2" 2 (5 3 (. 2#342#3/ 3 (( 2 $ 6 77 " 8 $9 1( $ :$ 68 .;* '0 ! , 1!) 2" !!! 3 - ! '4!$)% (T = -40C to +85 C, V = 2.0 V to 5.5 V) - ! Crystal !5! < < Crystal oscillation frequency 1 # - 10 MHz 3( 3 Ceramic < < Ceramic oscillation frequency 1 - 10 3( 3 External clock < < X input frequency 1 - 10 RC < < r = 35 K, V= 5 V 2 6 - ! !57 $% (T= -40C to +85C, V = 2.0 V to 5.5 V) - ! Crystal V = 4.5 V to 5.5 V V = 2.0 V to 4.5 V Ceramic External clock Stabilization occurs when V is equal to the minimum oscillator voltage range. X input high and low level width (t, t) - 50 - - - # - 10 30 4 - ns ms 7 $8 / 2 5 # '3 % # 5 # $.990 () < 41 % '3 !5 8 - ! '4!$)% (T = -40C + 85C, V = 2.0 V to 5.5 V) - ! Crystal !5! < < C1 = 33 pF, C2 = 33 pF 32 # 32.768 35 kHz 3( 3 * - ! $! %7 $% (T= 25C, V = 2.0 V to 5.5 V)) V = 4.5 V to 5.5 V V = 2.0 V to 4.5 V - - # 250 - 500 2 ms s 7 $8 /2 5 # '3 $ !"! ! ( T = - 40 C + 85 C, V = 2.0 V to 5.5 V) Liquid Crystal drive Voltage V Connect a 1M Load resistance Between V and V (No pannel load) LCON.7-.5 = 0 LCON.7-.5 = 1 LCON.7-.5 = 2 LCON.7-.5 = 3 LCON.7-.5 = 4 LCON.7-.5 = 5 LCON.7-.5 = 6 LCON.7-.5 = 7 V Connect a 1Mohm load resistance between V and V (No panel load) Connect a 1Mohm load resistance between V and V (No panel load) Connect a 1Mohm load resistance between V and V (No panel load) VLDCON.1-.0 = 00B VLDCON.1-.0 = 01B VLDCON.1-.0 = 10B VLDCON.1-.0 = 11B VLD Circuit Response Time VLD Operating Current Voltage Regulator and Booster Consumed Current TB IBL IVB Fw = 32.768kHz - V = 3.0V LCON.7-.5=4-7 Display on with capacitor bias 2 x V x 0.9 3 x V x 0.9 4 x V x 0.9 2.3 2.6 3.2 4.4 - - - Typ. x 0.9 # 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 - 2 x V x 1.1 3 x V x 1.1 4 x V x 1.1 2.5 2.8 3.4 4.6 1.0 10 10 mS A Typ. x 1.1 V V - V - VLD Voltage 2.4 2.7 3.3 4.5 - - 5.0 : $/( ( 2 0 ) # ( /;"*2 $( 9/$9 :/ %!"! ! LVR Voltage high V 2.4 2.8 4.0 2.0 2.4 3.2 10 0.5 V= 5V +/- 10% V= 3V 65 45 100 80 2.2 2.6 3.6 2.4 2.8 4.0 S S A # V LVR Voltage low V Power supply voltage rising time Power supply voltage off time LVR circuit consumption current T T I " 6#!/;-++#!;:<82 " ' &( ) '6 9/$9 :/ % +6 (= => * 5$6 %=> 2 (= ( / . % 1 11 ' / 6" -0 +,()% ? 6 ' -#/ The S3C8238/C8235 microcontroller is currently available in 64-SDIP, 64-QFP, 64-LQFP package. ! "#$ "#$ "#$ The S3F8235 single-chip CMOS microcontroller is the Flash MCUversion of the S3C8235 microcontroller. It has an on-chip Flash MCU ROM instead of a masked ROM. The Flash ROM is accessed by serial data format. The S3F8235 is fully compatible with the S3C8235, both in function and in pin configuration. Because of its simple programming requirements, the S3F8235 is ideal as an evaluation chip for the S3C8235. RESET ! ! ! ! ! ! ! ! ! RESET ! ! ! ! ! RESET ! ! ! ! !"# $%%&'(%)(*+,-)./ /0,$ 1 P0.3 1 SDAT 1% 14 % *. I/O % Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for FlashROM cell writing (indicates that FLASH MCU enters into the writing mode). When 12.5 V is applied, FLASH MCU is in writing mode and when 5 V is applied, FLASH MCU is in reading mode. (Option) Chip Initialization Logic power supply pin. Vshould be tied to +5 V during programming. P0.4 V SCLK TEST 15 20 I/O I RESET V/V RESET V/V 23 16/17 I - !"# 0%$%%& ( 0 0, Program Memory Operating Voltage (V) FLASH MCU Programming Mode Programmability 2.0 V to 5.5 V V = 5 V, V(TEST) = 12.5 V User Program multi time Programmed at the factory 16K-byte Flash ROM 2.0 V to 5.5 V 0 16K-byte mask ROM .-)!12/.-03)0!-) !0 When 12.5 V is supplied to the V (TEST) pin of the S3F8235, the FlashROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. !"# .$/%( #%0 4 5V 4!- ! )-2* 5V 12.5 V 12.5 V 12.5 V 0 0 0 1 (( 56 0000H 0000H 0000H 0E3FH )*+ 1 0 1 0 Flash ROM read Flash ROM program Flash ROM verify Flash ROM read protection /%( !"# 0-##0, (T= -40 C to +85C, V = 2.0 V to 5.5 V) Operating voltage 7"%# V V V Input low voltage V V 0%(% f = 8 MHz f= 4 MHz Input high voltage All input pins except V X XT All input pins except V X XT / 2.7 2.0 0.8 V V-0.1 - !7$ - - - - - 0.2 V 0.1 /8 5.5 5.5 V ' V !"# 0-##0,0%( (T= -40C to +85C, V = 2.0 V to 5.5 V) Output high voltage 7"%# V V V Output low voltage V V V Input high leakage current I I Input low leakage current I I Output high leakage current Output low leakage current Oscillator feed back resistors Pull-up resistor I I R R R COM output voltage deviation SEG output voltage deviation V 0%(% V= 2.4 V; I = -4 mA Port 0.4 only V= 5 V; I = -4 mA Port 3 V= 5 V; I = -1 mA All output pins except P0.4,P3 V = 2.4 V; I = 12 mA P0.4 only V = 5 V; I = 15 mA P3 V = 5 V; I = 4 mA All output pins except P0.4,P3 V = V All input pins except I V = VX XT V = 0 V All input pins except I V = 0 V, X XT V= V All I/O pins and Output pins V= 0 V All I/O pins and Output pins V= 5.0 V T= 25 C X = V, X= 0 V V = 0 V; V= 5 V 10 % Port 0,1,2,4 T = 25C V = 0 V; V!!= 5 V 10% T=25 C, only V = V = 4 V (V -COMi) IO = 15 p-A (i = 0-3) V = V = 4 V (V -SEGi) IO = 15 p-A (i = 0-23) - - 800 25 110 - - - 1000 50 210 60 - - - - / V- 0.7 V- 1.0 V - 1.0 !7$ V- 0.3 - - 0.3 0.4 0.4 - /8 - - - 0.5 2.0 2.0 3 20 -3 -20 3 -3 1200 100 310 200 mV k A ' V V - 60 200 !"# 0-##0,0%#(( (T= -40 C to + 85 C, V = 2.0 V to 5.5 V) Supply current 7"%# I 0%(% V= 5 V " 10 % 8 MHz crystal oscillator 4 MHz crystal oscillator V= 3 V " 10 % 8 MHz crystal oscillator 4 MHz crystal oscillator I Idle mode: V = 5 V " 10 % 8 MHz crystal oscillator 4 MHz crystal oscillator Idle mode: V = 3 V" 10 % 8 MHz crystal oscillator 4 MHz crystal oscillator I Sub operating: main-osc stop V= 3 V " 10 % 32768 Hz crystal oscillator Sub idle mode: main osc stop V= 3 V " 10 % 32768 Hz crystal oscillator Main stop mode : sub-osc stop V= 5 V " 10 % V= 3 V " 10 % / - !7$ 12 4 3 1 3 1.5 1.2 1.0 40 /8 25 10 8 5 10 4 3 2.0 80 A ' mA I 7 14 I 1 0.5 3 2 #$ %$ $$ $ $ &$ ' $$$ $ $ ($)% $% * $)% *$ % $+!, ) $ - $$)% * ., ) / , .., 0 (% $$,1 $ $ %$( 2) 3& !"# 4) %94%#)00, LVR Voltage high 7"%# V !0%(% / 2.4 2.8 4.0 2.0 2.4 3.2 10 0.5 V= 5V +/- 10% V= 3V 65 45 100 80 2.2 2.6 3.6 2.4 2.8 4.0 !7$ /8 ' V LVR Voltage low V V Power supply voltage riseing time Power supply voltage off time LVR circuit consumption current T T I S S A 4('560..('6789 +$ $ , $ % " " " " 4) %94%#)! +36#")'9 #$% !#$ ;(+3<#")'- $ #$% &''()#*("+,-#./ 0102&2#013"4&5"0*1#5(*56#7# #8#*350((+"*4#94-:&-15) .$4%#) Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. ! %! $# "#$ ! % ! # ! () * & '$ ! !"#$ "%&' ( )* The TB8238/5 target board is used for the S3C8238/C8325/F8235 microcontroller. It is supported with the SMDS2+, Smart Kit and OPENice. # 53 66 73 (( ! 73 ,/4++ /.. /.. -+.+ + -+. / + +0.12 (. (3* + 0 0/ ++, ( )*$ $!"#$ " $+,-, " ".# ( )* /0.12/ ". # 53 66 ! 3 3 3 7 # 53 66 ! $# 3$ " !44" . The SMDS2/SMDS2+ supplies V to the target board (evaluation chip) and the target system. (8 ! 3 3 $# 3 7 The SMDS2/SMDS2+ supplies V only to the target board (evaluation chip). The target system must have its own power supply. $+,-, " ".#2!3$ "%."&",5' 3$ " $# /0.12/ ". (34 3 3 !44" . The SMDS2+ supplies 5V to TB8238/5 target board (S3E8230). So, the target system be operated by 5V. 3 3 3 7 (34 3 3 3 3 3 7 !"#$ %&'()*+,- . $# The SMDS2+ supplies 3V to TB8238/5 target board (S3E8230). So, the target system be operated by 3V. & !% ' In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. $+,(6&,, " " /7/ " 7 3$ " 7 $# The Yellow LED is ON when the evaluation chip (S3E8230) is in idle mode. The Red LED is ON when the evaluation chip (S3E8230) is in stop mode. RESET (89"!"" .%:9;:9'# ( )* -+.+ + -+. / 9 :;0/< #:0 + 0 0/ 8(! ( )! (*) (*+$3 !$+,.#<8=$>$ $# -+. / -+.+ + 0 0/ + |
Price & Availability of S3F8235
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